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Blog 555 Voltage Controlled Oscillator
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  • Author Author: jc2048
  • Date Created: 13 Jun 2022 8:48 AM Date Created
  • Views 7317 views
  • Likes 10 likes
  • Comments 21 comments
  • timer
  • analogue design
  • vco
  • jc2048
  • 555
  • voltage controlled oscillator
Related
Recommended

555 Voltage Controlled Oscillator

jc2048
jc2048
13 Jun 2022
555 Voltage Controlled Oscillator

In the last blog, I used a 555 timer to make a simple oscillator. It used an
additional transistor, as a current source for the capacitor charging, in place
of the resistor that would usually be used. Although the blog focused on the
linear nature of the ramp and the resulting sawtooth waveform, my real interest
was slightly different as I wanted to use it as a VCO (Voltage Controlled
Oscillator).

Here I'm taking that circuit and adapting it so that I can control the current.
I need the control input to accept voltages in the range of 0-3.3V and to be a
very high impedance as it will be controlled by the voltage across a capacitor
(hopefully without discharging it). This is the circuit I ended up with.
image
On the right we still have the transistor and emitter resistor that function as
a current source, but now, instead of the base voltage being fixed by a
potential divider, it can be adjusted by the op amp. To the left, I have a
mirror image of the transistor and emitter resistor. Although the transistors
won't match exactly, the currents in the two 620 resistors will be approximately
the same. The current in the left 620 flows down through the transistor and
mostly out of the collector where it develops a voltage across the 3k3 resistor
that can be read by the op amp. That then gives voltage feedback that's
equivalent to the current that's flowing down into the capacitor. Final step is
for the op amp to compare that with the control voltage going in and drive the
bases in such a way that the two match. Op amps are good at that kind of thing,
particularly when you get the two inputs the right way round! (Yes, initially I
managed to overlook the inversion in the feedback path given by the transistor.)

It's not the most inspired piece of design ever and you probably wouldn't want
to use it for instrumentation (V -> f converter), but for what I want it will
suffice, though there is one snag with it which I will need to work around.

Here's a graph of the resulting frequency for different control voltages.
image
It's fairly linear, though there's a slight offset (it doesn't look like it
passes through the origin: thinking back, it's possible I had a 'scope probe on
the timing capacitor stealing some of the current, though a bipolar 555 will be
biasing it a little as well). The range is also somewhat limited. At the lower
end it becomes increasingly jittery when the frequency gets down to a few
hundred Hertz, presumably because of the low currents involved, so maybe two
decades at best without some more work.

If I tell you what the snag is - the oscillator stops with a control voltage of
0V, meaning there will no longer be edges in the output waveform - you may be
able to guess where I'm going for part three.

Next blog: 555 Phase-Locked Loop (PLL)

If you found this interesting and would like to see more blogs I've written, a
list can be found here: jc2048 blog index

References
[1] https://www.st.com/en/clocks-and-timers/ne555.html
[2] https://www.ti.com/lit/ds/symlink/ne555.pdf

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Top Comments

  • jc2048
    jc2048 over 3 years ago in reply to jc2048 +1
    Same VHDL design seems fine with my Brevia 2 board (XP2 FPGA with Diamond 3.12 IDE). Here's the 555 ramp waveform locked to 10kHz divided down from the board oscillator. Lots of jitter, though. I wasn…
  • jc2048
    jc2048 over 2 years ago in reply to msk167

    The two subsequent blogs have more complete circuits.

    If you use the one in the blog of the whole frequency synthesizer and leave out the phase comparator part, I think that will get you what you want.

    /technologies/555-timers/b/blog/posts/555-frequency-synthesizer

    Be aware that there was some kind of latch-up that the current source could get itself into that I never bothered to sort out (these blogs were just me fooling around with a 555, they aren't meant as tutorials or project builds).


    If you want a cheap VCO for an actual project, rather than just experiemnting for interest, you might do better to look at using the one in a HC4046.

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  • msk167
    msk167 over 2 years ago

    Dear 555 timers group.

    I am interested in building this vco ramp generator with the neat voltage control circuit.

    I am having some difficulty seeing how this new op amp controlled circuit replaces the voltage divider constant current source. I get that there is a replacement but it looks like the 555 connections are slightly modified.

    Could you please send a schematic that shows the op amp and two transitor control circuit connected to the 555 circuit.

    Thank you.

    msk167

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  • jc2048
    jc2048 over 3 years ago in reply to Jan Cumps

    The clocked flip-flop (FDRE) isn't a problem - that's the last part of generating the reference waveform to lock to. The line of LUTs below it is the phase comparator. My guess, and it is just a guess, is that it would work. One thing that looks a little wrong is the in_vco signal being distributed to so many LUTs. It only needs to go to one. But that might be something to do with the way the device routing works. It may be more optimal in routing terms to connect that and not use it rather than to organise a fixed level to hold an unused input. 

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  • Jan Cumps
    Jan Cumps over 3 years ago in reply to Jan Cumps

    ( ⇑ this was supposed to go to your pll blog)

    FDRE is a D flip-flop with clock Enable and synchronous Reset

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  • Jan Cumps
    Jan Cumps over 3 years ago

    I ran your design through the Vivado tools, with Spartan-7 selected as FPGA.
    Synthesized schematic:

    image

    Implemented:
    image

    readable PDF.

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