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Blog Hercules microcontrollers, DMA and Memory Cache
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  • Author Author: Jan Cumps
  • Date Created: 2 Jan 2016 9:17 PM Date Created
  • Views 4922 views
  • Likes 6 likes
  • Comments 20 comments
  • hercules_launchpad
  • texas_instrments
  • cache
  • arm_cortex
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Hercules microcontrollers, DMA and Memory Cache

Jan Cumps
Jan Cumps
2 Jan 2016

DMA and memory cache don't always play nicely together.

I had an issue when trying to use serial communication and DMA on a TI Hercules controller. The DMA data wasn't appearing in my read buffers.

TI's application specialists helped me to resolve my issues. It was related to ARM memory cache settings.

I've written a step-by-step guide on the hackster.io forum on that subject.

 

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Due to the subject, this hasn't turned into an easy-to-read novel. I hope it may help fellow developers struggling with similar issues.

 

When you're playing with DMA, you think everything is working ok, and you don't see any data written to your variables, this post may be worth looking into.
It's based on an SCI example, but applicable in many DMA situations.

 

Default Cache configuaration is write-back:

image

For DMA relevant buffers, you can specify a chunk of RAM with write-through configuation.

image

There's more to do than just setting aside a portion of the memory. Check the video for a quick overview, and the hackster.io blog post for a step-by-step explanation with a working project attached.

 

The Series
0 - Buffers and Parallel Data Lines
1a - Buffers and DMA
1b - SPI without Buffers
2 - SPI with Buffers
3a - SPI with DMA
3b - SPI with DMA works
4a - SPI Master with DMA and Parallel Data Lines
Hercules microcontrollers, DMA and Memory Cache
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Top Comments

  • clem57
    clem57 over 9 years ago +2
    Thank you on describing cache coherence with DMA. This is a common occurrence since the microcontroller own's cache resource on the chip and not the external DMA circuits which can only see RAM. Clem
  • clem57
    clem57 over 9 years ago in reply to Jan Cumps +2
    i found him! Clem
  • DAB
    DAB over 6 years ago in reply to Jan Cumps +2
    It still sounds like it steals CPU cycles unless there is a full isolation with separate address and data lines into the memory. I have seen designs with that approach so that the I/O processor can access…
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  • Naveen_R
    Naveen_R 4 months ago

    Hi, 
    Thanks for this blog, where I found a clear-cut explanation on Cache coherence with DMA.

    I could not be able to find the link for 4b which is a continuation of this blog, can you please share that link.

    Kind Regards, 
    Naveen

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  • Naveen_R
    Naveen_R 4 months ago

    Hi, 
    Thanks for this blog, where I found a clear-cut explanation on Cache coherence with DMA.

    I could not be able to find the link for 4b which is a continuation of this blog, can you please share that link.

    Kind Regards, 
    Naveen

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