Flipping out on flip-flop basics

Question

Hey folks, I am working my way through Forrest Mims' Digital Logic Projects Workbook 2 and stumbling on understanding basic D-type flip-flop operations. I hope someone can help me understand where I am getting lost.

Mims presents this explanation of a 4013 D-type flip flop:

which, as I understand it, on the rising edge of a clock pulse Q1 gets set when D is set. (By the way, why does he use Q1 and Q2 in the truth table and Q and ~Q (I don't know how to write a Q with a line over it) in the schematic??). He presents a basic flip flop circuit to demonstrate this :

Ok I get when you set D in this circuit with the toggle switch manually, Q1 gets set high (1) with the rising clock pulse!

Now the circuit I am working on:

The circuit works as it should, lighting up LED's 1,2,3,4 in sequence. Ok. However, when I put a logic probe on pin 5 of the 4013 (D1) with the rising clock pulse starting from 0, D1 is 0 (low) but Q1 is 1 (high). I don't understand why Q1 is set when D1 is low. Here is the truth table I came up with but it seems to me from the truth table in the image at the top of this post, on rising clock pulse when D1 is 0, ~Q should get set to 1 (high). I feel like I am missing the sequence of how the outputs get changed but I don't know what... Help!

Thanks!

Robert Opalko

Message was edited by: Robert Opalko

wolfgangfriedrich · Accepted Answer

The short answer is, that the ~Q output (pin2) is connected to the D input (pin5). When the rising edge happens and after the propagation delay of the flipflop the outputs toggle according to the D input. When D is high, Q goes high and ~Q goes low, which loops back to the D input.

The logic probe would not show this relationship as the prop delay is only some nanoseconds.

The long answer would require a timing diagram.

If you have an oscilloscope, look at the clock, D and Q,~Q signals and trigger on the clock.

- W.

dougw · Answer

As wolfgangfriedrich points out the FF is operating as it should. When the clock rising edge occurs whatever is at D gets latched to Q. In this case /Q gets latched as the inverse of Q, and it is connected to D, so D immediately toggles from what it was when the rising edge occurred. This new state at D does not get latched until the next rising edges, so it is mostly not equal to Q, because as soon as Q gets latched, /Q inverts D. Q matches D only for the brief time between the rising clock edge and the time it takes /Q to get its new value.

The D FF is actually hooked up as a T (toggle) FF.

gdstew · Answer

Propagation delay, the amount of time an output (Q or ~Q) takes to change after a change in an input (D and clock) for 4000 series ICs is measured in 10s to 100s of nanoseconds depending on the operating voltage. So without an

oscilloscope or logic analyzer you will not be able to see any difference. There is also something called set up time which is the amount of time that the D input must be stable before the clock input makes a low to high transition

and clocks in what is on the D pin. Also just a bit of clarification the D pin is not actually connected to the Q or ~Q pin, there are several logic gates in between that form the flip-flop. You might want to google CD4013 and look at

the data sheet to get a better idea of what it takes to make a D type flip-flop.

wolfgangfriedrich · Answer

And your truth table is correct for the settled state (time > all propagation delays of all stages) after the rising edge, but it is incomplete. To understand the full circuit operation you would need to draw a state diagram. The states would show all output signals and the transitions between the states would be initiated by the rising clock edges and depend on the input D-signals.

As an unrelated side note, I don't like the example very much as it is an asynchronous circuit with the output of one flip-flop feeding into the clock of the following flip flop, which is much harder to follow and understand than a synchronous one (all FFs get the same clock and change state at the same time). This is hopefully explained soon in the next chapter of the book.

PS: Is the whole book written in XKCD font?

fmilburn · Answer

RE XKCD font: Forrest Mims’ work was meticulously handwritten and had hand drawn illustrations - he was famous for it. He does not have a formal engineering or scientific background so his work does not always follow the route we might expect.

gdstew · Answer

You might want to look into Karnaugh maps. They are used to simplify generating combinational logic circuits as well as simplifying the circuits themselves.

dougw · Answer

Excellent question. There are many ways to solve the requirement. People will tend to use what they have used in the past, some would use a microcontroller, some would use a counter and a ROM, some would use an FPGA, some would use daisy-chained one-shots, some would use a Johnson counter, etc. But to solve it with just basic knowledge of logic gates without knowing the solution is what engineering is all about. One method is to search the internet for similar solutions. One method is to look through datasheets until you see something that solves a part of the problem. The classic engineering approach is to break the problem down into smaller problems until the solutions are obvious to your level of knowledge. If you have some knowledge about state machines, you could start by defining all the states of the system and how successive states relate to previous states. And then work out the logic required to transition from one state to the next. Some purists would use a top-down design approach, others would use a bottom-up approach. but most would use a combination. For example they might start with something they know that generates a sequence of states, such as a binary counter. If you have a counter that counts to 4, then each state corresponds to a different count on the counter, so to have each counter state turn on a different LED is just a matter of figuring out what logic is needed to recognize each count. For example if all bits are off the first LED might illuminate - this is just a NOR gate. Incidentally - this is the logic that is inside a Johnson counter - which does the sequential outputs in one chip.

gdstew · Answer

I've been busy for a while and have some catching up to do here. I don't know how I messed this up but I should have said the low to high clock transition if you want to see the timing relationship between the clock pulse and the Q or ~Q output. That is the clock edge used to clock in what is on the D input. My bad! Looking at some of the new scope traces you can clearly see the differences in the signal timing so you are on the right track. If switch the D scope trace to the Q output you should be able to see the propagation delay from the rising clock edge to the Q output change. One thing that Doug didn't get quite right is the clock threshold voltage needed to clock in the data. On CMOS ICs like the 4013 (and 74HC series) this voltage is higher than ~2V which is the threshold for TTL compatible ICs. The spec sheet for the 4013 says 3.5V is the minimum for a 5V power supply so I'm going to guess it needs to be around 3.75 - 4V min. for the 6V supply shown in the book schematics. Ignorance is easily fixed by learning and you are clearly making an effort to learn. It really helps that you have the tools to dig deeper when you need to. My only problem here is that I have to attempt to explain multifaceted electronic concepts in writing. And there are very few circuits which do not require understanding multiple electronic concepts. For me at least it is much easier to do this with a back and forth conversation with a white board close by just in case. Conversation also usually allows me to catch my mistakes when or at least shortly after I make them instead of hours later (ouch, that one hurt).

gdstew · Answer

At 6V you are going to have to sample at 100ns or less to see a difference, probably 50ns minimum, 20ns to get a really good look. Also you should trigger on the high to low clock transition.

In Pics 1 and 3 you are triggering on the data.

dougw · Answer

Can you show The rising edge of the clock and the D input at maximum time resolution? When the clock edge is detected at about 2 V the value of D gets latched to Q. If D changes after that, and it will because /Q will change, it will not change Q. You want to look at the voltage at D when the clock is first recognized as going high.

dougw · Answer

That is a good scope shot. It shows that D is stable and low when the clock goes high. This latches low on Q and high on /Q. When /Q goes high, D goes high, because they are connected. Because there is no rising clock edge after D goes high, Q stays low. The delay between when the clock goes high and when D goes high is the propagation delay through the FF. If you capture what happens when D is high and a rising clock happens, D should stay high until after the clock goes high and then go low after about the same propagation delay..

opalko · Answer

(Yes, as fmilburn said, the entire book is written this way, as are the other ones I have seen.. Getting Started in Electronics, Mini Notebooks etc. As for explaining it in the next chapter, well,.. Forrest doesn't explain the circuits much, if at all. It is left to the reader to build the circuit and figure out what is going on, which is what led me here!!!)

With that being said, I should explain what I was trying do. Rather than look at the blinky lights go on 1,2,3,4 - say "neat" and move on to the next project I was trying to figure out how the 4001 quad NOR gate was getting the signals to turn the LED's on in that sequence. So I was trying to reverse engineer the circuit back to the truth table level and the results didn't match with what Mims shows in this pic:

since wolfgangfriedrich said my TT was correct, I am still lost, lol! So is Mims TT incomplete as well? (Don't even get me started on understanding the 4013 changes in the second part 2/2 with clock and Q2 and ~Q2...)

I will add some scope screen captures I took after you suggested using scope instead of logic probe. I must not have captured or I don't know what I am looking for as it looks to me like the clock - Q - ~Q - D all change at the same time; I would have thought one would precede the others. I should make clear I am a complete novice with using an oscilloscope, and my cheapee Siglent 1202X-E may not be enough to measure what I need to see.

Pic 1: Yellow is clock signal, Pink is Q

Pic2: Yellow is clock signal, pink is ~Q

Pic 3: Yellow is D, pink is Q

Flipping out on flip-flop basics

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