Flipping out on flip-flop basics

Ok, clock yellow, triggered on falling edge. Pink is D / ~Q. 500ns is the limit on this scope.....

Can you show The rising edge of the clock and the D input at maximum time resolution?

When the clock edge is detected at about 2 V the value of D gets latched to Q.

If D changes after that, and it will because /Q will change, it will not change Q.

You want to look at the voltage at D when the clock is first recognized as going high.

Ok I hope this is correct. Yellow clock, pink D.  I have a long way to go learning how to use my scope

If nothing else I am learning to use my scope better (I think). I was wrong about the limit, here is 10ns... I haven’t figured out why I don’t see D climbing when clock is at 2V; I know I still have scope settings wrong somewhere..

Thank you for the answers and putting up with my ignorance on this stuff!

That is a good scope shot. It shows that D is stable and low when the clock goes high.

This latches low on Q and high on /Q.

When /Q goes high, D goes high, because they are connected.

Because there is no rising clock edge after D goes high, Q stays low.

The delay between when the clock goes high and when D goes high is the propagation delay through the FF.

If you capture what happens when D is high and a rising clock happens, D should stay high until after the clock goes high and then go low after about the same propagation delay..

I've been busy for a while and have some catching up to do here. I don't know how I messed this up but I should have said the low to high clock transition if you want to see the timing relationship between

the clock pulse and the Q or ~Q output. That is the clock edge used to clock in what is on the D input. My bad! Looking at some of the new scope traces you can clearly see the differences in the signal

timing so you are on the right track. If switch the D scope trace to the Q output you should be able to see the propagation delay from the rising clock edge to the Q output change. One thing that Doug didn't

get quite right is the clock threshold voltage needed to clock in the data. On CMOS ICs like the 4013 (and 74HC series) this voltage is higher than ~2V which is the threshold for TTL compatible ICs. The spec

sheet for the 4013 says 3.5V is the minimum for a 5V power supply so I'm going to guess it needs to be around 3.75 -  4V min. for the 6V supply shown in the book schematics.

Ignorance is easily fixed by learning and you are clearly making an effort to learn. It really helps that you have the tools to dig deeper when you need to. My only problem here is that I have to attempt to explain

multifaceted electronic concepts in writing. And there are very few circuits which do not require understanding multiple electronic concepts. For me at least it is much easier to do this with a back and forth

conversation with a white board close by just in case. Conversation also usually allows me to catch my mistakes when or at least shortly after I make them instead of hours later (ouch, that one hurt).

No worries -I am thankful to have folks take the time to reply with answers and explanations!

So I think I understand the delay between clock, D, and Q and also that my TT is incomplete and I really need a state diagram showing the changes,... but I am back to my original question: you want 4 LED's to light in a sequence..how do you get from that goal to knowing to use the 4001 and 4013 (and 4049)? Is it done with truth tables?

Excellent question.

There are many ways to solve the requirement.

People will tend to use what they have used in the past, some would use a microcontroller, some would use a counter and a ROM, some would use an FPGA, some would use daisy-chained one-shots, some would use a Johnson counter, etc.

But to solve it with just basic knowledge of logic gates without knowing the solution is what engineering is all about.

One method is to search the internet for similar solutions.

One method is to look through datasheets until you see something that solves a part of the problem.

The classic engineering approach is to break the problem down into smaller problems until the solutions are obvious to your level of knowledge.

If you have some knowledge about state machines, you could start by defining all the states of the system and how successive states relate to previous states. And then work out the logic required to transition from one state to the next.

Some purists would use a top-down design approach, others would use a bottom-up approach. but most would use a combination.

For example they might start with something they know that generates a sequence of states, such as a binary counter. If you have a counter that counts to 4, then each state corresponds to a different count on the counter, so to have each counter state turn on a different LED is just a matter of figuring out what logic is needed to recognize each count.

For example if all bits are off the first LED might illuminate - this is just a NOR gate.

Incidentally - this is the logic that is inside a Johnson counter - which does the sequential outputs in one chip.

You might want to look into Karnaugh maps. They are used to simplify generating combinational logic circuits as well as simplifying the circuits themselves.