UART custom AXI4 Lite IP

I published an example for a simple custom SPI driver that can help you. Look for "Creating an AXI-Lite IP block" for the driver section.

 Blog 4 - FruitVision Scale - FPGA-Based HX711 Driver for Precision Weighing with AMD PYNQ 

Other projects I published with AXI4 Lite implementation:

 Arty S7 50 ArtyBot Custom AXI4 Lite IP Peripheral for Sensing Motor Rotational Speed 

 AMD Zynq SoC MIDI Vintage Sound Synthesizer - Final 

Great share J!

Sorry for not responding sooner, I checked the box to email me when I got a response and the system neglected to do that.

Apologies, however, I lacked a crucial detail that I should have mentioned.  I want to use the UART that is connected to pins MIO10 and MIO11 (the JTAG/UART connections).  Those pins though, as the pin names imply, are PS pins.  While the example you gave is very helpful, it is like other examples I have found before.  I understand the surface process (create AXI4 Lite and it creates a toplevel and wrapper), however, I am unsure what logic I need to add to the wrapper as the toplevel simply the components of the design I created.  How many registers, how to declare slave logic, assign PS connections, find UART address, how to hook the AXI4 to the processing system.

I do hope that makes sense.  As a side note, I use VHDL, not SystemVerilog, so while I can read the design you shared, I would need to convert the logic.  Here is my program:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD_UNSIGNED.ALL;

ENTITY UART_TX IS
    PORT (clk : IN  STD_LOGIC;
          reset : IN  STD_LOGIC;
          tx_valid : IN STD_LOGIC;
          tx_data : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
          tx_ready : OUT STD_LOGIC;
          tx_OUT : OUT STD_LOGIC);
END UART_TX;

ARCHITECTURE Behavior OF UART_TX IS
TYPE state IS (IDLE, START, SEND, STOP);
SIGNAL currentState : state;

CONSTANT BAUD : STD_LOGIC_VECTOR (9 DOWNTO 0) := d"868";

SIGNAL bits : INTEGER RANGE 7 DOWNTO 0 := 7;
SIGNAL counter : STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0');

BEGIN
    PROCESS(ALL)
    BEGIN
        IF RISING_EDGE(clk) THEN
            IF reset THEN
                CASE currentState IS
                WHEN IDLE => IF tx_valid = '1' THEN
                    tx_ready <= '0';
                    tx_OUT <= '1';
                    currentState <= START;
                ELSE
                    tx_ready <= '0';
                END IF;
                WHEN START => IF counter = BAUD THEN
                    tx_OUT <= '0';
                    counter <= (OTHERS => '0');
                    currentState <= SEND;
                ELSE
                    counter <= counter + '1';
                END IF;
                WHEN SEND => IF counter = BAUD AND bits = 0 THEN
                    tx_OUT <= tx_data(bits);    
                    counter <= (OTHERS => '0');
                    currentState <= STOP;
                ELSIF counter = BAUD AND bits > 0 THEN
                    tx_OUT <= tx_data(bits);
                    counter <= (OTHERS => '0');
                    bits <= bits - 1;
                ELSE
                    counter <= counter + '1';
                END IF;
                WHEN STOP => IF counter = BAUD THEN
                    bits <= 7;
                    tx_ready <= '1';
                    tx_OUT <= '1';
                    counter <= (OTHERS => '0');
                    currentState <= IDLE;
                ELSE
                    counter <= counter + '1';
                END IF;
                END CASE;
            END IF;
        END IF;
    END PROCESS;
END ARCHITECTURE;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD_UNSIGNED.ALL;

ENTITY UART_RX IS
    PORT(clk : IN  STD_LOGIC;
         reset : IN  STD_LOGIC;
         rx_IN : IN  STD_LOGIC;
         rx_valid : OUT STD_LOGIC;
         rx_data : OUT STD_LOGIC_VECTOR (7 downto 0)
         );
END UART_RX;

ARCHITECTURE Behavior OF UART_RX IS
TYPE state IS (IDLE, START, RECEIVE, STOP);
SIGNAL currentState : state;

CONSTANT BAUD : STD_LOGIC_VECTOR (9 DOWNTO 0) := d"868";

SIGNAL bits : INTEGER RANGE 7 DOWNTO 0 := 7;
SIGNAL counter : STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0');

BEGIN
    PROCESS(ALL)
    BEGIN
        IF RISING_EDGE(clk) THEN
            IF reset THEN
                CASE currentState IS
                WHEN IDLE => IF NOT rx_In THEN
                    rx_valid <= '0';
                    currentState <= START;
                END IF;
                WHEN START => IF counter = BAUD / 2 THEN
                    counter <= (OTHERS => '0');
                    currentState <= RECEIVE;
                ELSE
                    counter <= counter + '1';
                END IF;
                WHEN RECEIVE => IF counter = BAUD THEN
                    rx_data(bits) <= rx_IN;
                    counter <= (OTHERS => '0');
                    IF bits = 0 then
                        currentState <= STOP;
                        bits <= 0;
                    ELSE
                        bits <= bits - 1;
                    END IF;
                ELSE
                    counter <= counter + '1';
                END IF;
                WHEN STOP => IF counter = BAUD / 2 THEN
                    bits <= 7;
                    rx_valid <= '1';
                    counter <= (OTHERS => '0');
                    currentState <= IDLE;
                ELSE
                    counter <= counter + '1';
                END IF;
                END CASE;
            END IF;
        END IF;
    END PROCESS;
END ARCHITECTURE;

What I need to do is take this logic and make an IP out of it, hook it up to the Zynq PS and then create a C program in Vitis to read and write via UART.

I'm not sure I understand what you're trying to do. I'd recommend you first look at how Vivado's block designer works. In this example, I simply instantiated a Zynq PS and then dragged the UART configuration from the board provided by the manufacturer.

After running block automation, the Zynq PS block will automatically expose the enabled UART as an AXI peripheral.

Then you can check how the AXI UART Lite implements something similar

AXI UART Lite v2.0 Product Guide (PG142) • Viewer • AMD Technical Information Portal

Forgive me I am still trying to get a better grasp on SoC fundamentals., I will try to explain better.  What I want to do is create my own IP for the UARTLITE.  I want to use the dedicated UART pins (M10 and M11) with my own AXI4 IP.  I want to use the UART program I created for the ZuBoard to utilize.  That way I can create my own functions in Vitis to display.  I know it sounds like a lot of extra work; on the other hand, I want to make as much original designs as possible.  What's the fun in just using premade IPs?  Essentially, I am trying to remake the wheel with my own version of the code.  I hope that makes more sense.