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  • Author Author: michaelkellett
  • Date Created: 30 Sep 2017 4:20 PM Date Created
  • Views 5831 views
  • Likes 10 likes
  • Comments 33 comments
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Gnarly Grey UPduino

michaelkellett
michaelkellett
30 Sep 2017

Following the mega useful suggestion from aventuri about the existence of this board I bought one because I couldn't find any other way to get hold of a Lattice UP5k FPGA chip in 48 pin QFN.

 

This is an interesting FPGA in that it has 5k LUTs, the usual block RAM (15kbytes), 4 single port RAMs totaling 128kbytes and 8 16 bit wide multipliers, all this in a 48 pin prototype friendly QFN package and quite cheap - if only anyone had them in stock.

 

The UPduino board has A UP5k, an absurdly large (32Mbit) flash for program storage, a three colour LED, power regulators and not much else. It is very cheap at $7.99.

 

The owner of Gnarly grey worked for Lattice for several years and thye are promoting the board on their website.

 

My board came very quickly from the US to here in the UK, no fancy packaging, just a poly (anti static) bag in a standard envelope.

 

I got it going today which took way longer than it should have done you can program the FLASH memory using standard Lattice software with an FTDI breakout board or cable I didn't have a board but I did have a  C232HD-DDHSP-0C232HD-DDHSP-0 cable(Farnell 2352017 To cut a long story short the cable won't work unless you reduce its length drastically I cut mine down to about 10cm long This is because neither the FTDI chip in the cable or the FLASH chip on the FPGA board expect to drive cables when the data changes on the output of the FLASH chip it cross couples into the clock signal due to the cable capacitance and the resulting clock glitch breaks the communications Crazily it took a 1GHz scope to debug the comms the FLASH chip is fast and the glitches are short

 

The hardware design of the board is truly dreadful - OK it was cheap but it is kind of amazing bearing in mind the makers' connections with Lattice. It breaks several of Lattice's design rules for this part.

 

There is almost no power supply decoupling on the board.

There is no ground plane and the ground is a spidery thin track weaving about the board.

Lattice recommend a filter to the FPGA PLL power pin - the UPduino has the series 100R resistor but does not have a capacitor on the FPGA side of the resistor to ground.

 

 

There is no precision oscillator on the board - the UP5k has its own rubbish 48MHz (+/- 10% for 0-85C)) oscillator on chip but this isn't good enough for a great many things. It's worth putting the oscillator on board so the fast clock doesn't have to have long wires.

 

I'll add to this blog if I do much more with the UPduino - it's tempting just to remove the FPGA and put it on my own board.

 

The supplied example files are pretty gruesome, possibly below even Lattice's pretty low standard for example code. The LED blink example is quite short but has not one single comment !

There is a Raspberry Pi IO expander example on GG's website - the key file in that is spi_gpio.v - oddly embellished with Lattice copyright stuff and dated 2010 - 310 lines of code - zero comments.

 

In summary this is great idea done badly: very badly.

 

It's not much use to pros -  no oscillator, dreadful design practice so won't give a good idea of any device limitations and is hopeless as a reference design. It's not much use for learning either -  the low price is great but the total lack of any kind of decent tutorial stuff is a huge negative.

 

So unless, like me, you just have to get hold of the UP5K, this isn't a very good buy - even at $7.99.

 

MK

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Top Comments

  • shabaz
    shabaz over 8 years ago +3
    I noticed this on their website, my underlining: I think they perhaps confused the idea of a legitimate good quality minimal-accoutrements development product as somehow being in conflict with not spending…
  • shabaz
    shabaz over 8 years ago +2
    It is weird, it doesn't make sense given the linkedin page of the author of that design, how come the design itself ( PDF schematic ) is so bad. I guess it shows how important an interview (and maybe even…
  • johnbeetem
    johnbeetem over 8 years ago +2
    Thank you for this review. It's sad that the board's electrical design is so poor. It's not that hard to do a decent PCB job, but one does have to have some experience. Memo to UPDuino: ground lines that…
  • vr2045
    vr2045 over 6 years ago

    Hello folks,

    Happy to report that the layout for the UPduino 3.0 is now complete and the design is uploaded on GitHub. This incorporates all the feedback I received and is summarized in the wiki page here. I created a blog that documents my analysis related to the PLL issue here.

    Thank you!

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  • vr2045
    vr2045 over 6 years ago in reply to michaelkellett

    Good suggestions Michael, thank you for the feedback!

    I'll try to migrate the design to Kicad and add an option to use the FTDI oscillator output. Also will follow recommendations on power supply for the FTDI and fpga. Probably will go to a 4 layer board to ensure clean power.

     

    Other changes being considered :

    - QWIIC/Grove connectors to allow for easy connection to the sensor ecosystem. PMOD is already supported.

    - Ability to program the CRAM on the FPGA without messing with soldering jumpers.

    - Programmable bank IO voltage of 1.8V (is currently 1.2V which is not at all common).

    - High speed SPI access capability over FTDI/pins to allow designs to exchange data at ~10Mbps. Beats a UART and could enable all kinds of interesting applications like using the fpga as a HW accelerator. Related to CRAM access.

     

    PS: The Tindie store is now open here: https://www.tindie.com/products/tinyvision_ai/upduino-v21-low-cost-fpga-board/

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  • michaelkellett
    michaelkellett over 6 years ago in reply to vr2045

    I just took a quick look at the schematic.

     

    It is good practice to have  a decoupling capacitor for every power pin, whilst this new design is better than the original it still doesn't have enough.

    (Neither the FPGA nor the FT232 are adequately decoupled).

     

    Linking the OSCOUT from the FT232 to the FPGA PLL input via a resistor would be nice, providing a decent 12MHz oscillator independent of the FT232 but able to clock it when required would be even better.

     

    The board files are Eagle - but Eagle is not open source of free (in any sense) - it would be much better (if you want to make this a truly open hardware product) to use Kicad.

     

    MK

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  • vr2045
    vr2045 over 6 years ago

    Hello folks,

     

    I’ve taken over the production of the UPduino’s from Lattice recently  (GitHub site is here) and would love to hear your feedback. WIll be sold on Tindie soon. I created a Survey for this but would also love to hear feedback from the community on how to make this a better platform.

    Thank you,

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  • Oldsirhippy
    Oldsirhippy over 7 years ago in reply to gjennings

    hi Grant,

     

    Your web site contact details do not work.

    Would you post how to get in contact with you please - I'm interested in your FPGA and digital image processing IP.

     

    Thanks

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