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The Art of FPGA Design Season 2 Post 29

fpgaguru

Can IIR FIlters Be Fully Pipelined? We have reached the final post in this series on LWDF IIR filters. I hope that I was able to convince you that many, if not all, of the perceived disadvantages of IIR filters can be addressed while maintaining thei...
- 27 Aug 2025
The Art of FPGA Design Season 2 Post 28

fpgaguru

Look Ma, no multipliers! The last LWDF IIR filter example I gave was unusual in the sense that it was multiplierless, all the coefficients were powers of two, which in FPGA hardware cost absolutely nothing. Of course, this restricts considerably the ...
- 19 Aug 2025
The Art of FPGA Design Season 2 Post 27

fpgaguru

Linear Phase IIR Filters? Part 3 Finally, the third and probably most efficient, but also least known and used way to achieve near linear phase IIR filters is the object of this post. Absolute linear phase, or equivalently constant group delay,...
- 18 Aug 2025
The Art of FPGA Design Season 2 Post 26

fpgaguru

Linear Phase IIR Filters? Part 2 The forward-backward method of turning any non-linear phase IIR into a "linear phase" one at a much lower hardware cost than the classic linear phase FIR implementation I showed in the previous blog post wor...
- 11 Aug 2025
The Art of FPGA Design Season 2 Post 25

fpgaguru

Linear Phase IIR Filters? Part 1 I hope everybody can agree by now that IIR filters, especially in their LWDF form, are at least interesting and worth a look. I mean, an order of magnitude on average less resources compared with an equivalent FIR has...
- 9 Aug 2025
The Art of FPGA Design Season 2 Post 24

fpgaguru

LWDF IIR Filter Design Examples If you made it this far through the math wilderness, congratulations, it's time now to put all that knowledge to good use and design some LWDF IIR filters. I will start with some simple ones first, graduating then ...
- 8 Aug 2025
The Art of FPGA Design Season 2 Post 23

fpgaguru

Implementing the First and Second Order All Pass Sections with DSP Primitives We are almost there now. We have the LWDF IIR filter architecture, which is much better then the classic biquad cascade: It is made out of two parallel all pass path...
- 7 Aug 2025
The Art of FPGA Design Season 2 Post 22

fpgaguru

LWDF IIRs I am finally ready now to discuss the LWDF IIR filter architecture. In a few words, such a filter consists of two parallel all pass sections, which differ in order by 1, which means that one path is of odd order while the other one is...
- 6 Aug 2025
The Art of FPGA Design Season 2 Post 21

fpgaguru

You cannot always trust AIs I asked four major AI chat bots the same question: "What is the most efficient way to implement IIR filters? Reply in 40 words or less." Here are the responses: Perplexity AI: "Use a cascade of second-order (bi...
- 5 Aug 2025
The Art of FPGA Design Season 2 - Post 20

fpgaguru

IIR Filters 101 I will try to keep the math side of things as light as possible but we cannot avoid it completely, so I will use the hand waving proof technique. If you have any doubts or questions about the statements made here without any proof, pl...
- 31 Jul 2025
The Art of FPGA Design Season 2 - Post 19

fpgaguru

Why IIR Filters? Now I am going to switch gears from FIRs to their poorer and much less famous cousins, IIR filters. Recursive or Infinite Impulse Response filters tend to have a very bad reputation and are rarely used compared with Non-Recursive, Fi...
- 26 Jul 2025
AMD Spartan UltraScale+ FPGA in action

bhfletcher

It's Alive! If you haven't had a chance to see the AMD Spartan UltraScale+ FPGA in action, here is a great opportunity. The AMD SCU35 board has the XCSU35P device on it. While not released to the public yet, we have many that are working with early a...
- 20 Jul 2025
ZUBoard High Speed IO (J6) used by MIPI CSI-2 Rx IP on PL side

JChen

I have two questions before to purchase ZUBoard 1CG + Avnet The dual-camera mezzanine: 1) For camera image processing, can I use Xilinx DPU IP on PL side from this ZUBoard development board? 2) Is this ZUBoard development board to support M...
- 19 Jun 2025
Lattice iCEstick EVB Generating Three-Phase Sinewaves with Sigma-Delta DACs Using iCEcube2 and VHDL

jc2048

Introduction A good while back, when I purchased an ADALM1000, I realised that Farnell had the Lattice ICEstick back in stock so I bought one of those too. I thought it would be nice to do a simple project, with a few of my impressions of the board ...
- 15 Jun 2025
Mini Project for learning HDL/Verilog: Making a part of a very small processor

Aritra2k2

Hii all, This is me first time posting here on element14. I recently completed a Hardware Description of a part of a processor in Verilog. In this mini project, I ensured the datapaths, added 7 registers ( 6 normal and 1 special). The special registe...
- 7 Apr 2025
RPI Camera Fun with Zynq-UltraScale+ : LIBCAMERA

albertabeef

Introduction This project is part 4 of a N part series of projects, where we will explore how to integrate Raspberry Pi cameras on Zynq-UltraScale+ boards. Part 1 : RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2 Part 2 : RPI Camera Fun ...
- 3 Feb 2025
RPI Camera Fun with Zynq-UltraScale+ : White Balance

albertabeef

Introduction This project is part 3 of a N part series of projects, where we will explore how to integrate Raspberry Pi cameras on Zynq-UltraScale+ boards. Part 1 : RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2 Part 2 : RPI Camera Fun ...
- 27 Jan 2025
RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V3, HQ, AI

albertabeef

Introduction This project is part 2 of a N part series of projects, where we will explore how to integrate Raspberry Pi cameras on Zynq-UltraScale+ boards. Part 1 : RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2 Part 2 : RPI Camera Fu...
- 29 Dec 2024
RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2

albertabeef

Introduction This project is part 1 of a N part series of projects, where we will explore how to integrate Raspberry Pi cameras on Zynq-UltraScale+ boards. Part 1 : RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2 Part 2 : RPI Camera Fu...
- 23 Dec 2024
Tria Vitis Platforms — Adding support for ROS2

albertabeef

Introduction This project is part 5 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the source co...
- 25 Nov 2024
Tria Vitis Platforms — Adding support for Hailo-8

albertabeef

Introduction This project is part 4 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the source co...
- 18 Nov 2024
Tria Vitis Platforms — Adding support for Vitis-AI 3.5

albertabeef

Introduction This project is part 3 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the source co...
- 11 Nov 2024
Tria Vitis Platforms - Creating a Common Platform

albertabeef

Introduction This project is part 2 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the source co...
- 4 Nov 2024
Tria Vitis Platforms — Building the Foundational Designs

albertabeef

Introduction This project is part 1 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the source co...
- 28 Oct 2024
How to build Xilinx Default HDL Project for zcu102 in Window?

ijazmuhammad

Video link: https://studio.youtube.com/video/nSbfVxOD5vk/edit Courtesy to: https://wiki.analog.com/resources/fpga/docs/build Prerequisites: Prerequisites: Vivado installed Steps to build: Cygw...
- 17 Oct 2024