This is a supporting post for Part 2: Add the Accelerated IP to a Vivado design.I'm untangling the different data streams.There are 3 types of data exchanged between the FPGA and ARM parts of the Zynq:
"Business Data": the inputs and outputs to...
I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience.
Use the Accelerated function in Software
In part 1, we made the hardwa...
I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience.
Register the IP and Use it in Vivado
In part 1, we made the hardware a...
PYNQ now supports Vivado and Vitis HLS version 2020.2 (since PYNQ 2.7).Time to re-check the hardware accelerator mechanisms, with DMA. This workflow has now stabilised.
Hardware Acceleration is the technique to implement program logic insi...
Yesterday, the PYNQ community released version 2.7 of the the PYNQ OS.SD Card images are available for download.
What's new:
Vivado, Vitis HLS version 2020.2
Python 3.8
Additional boards supported
Composable overlay pipeline
Petalinux 2020.2, U...
I was asked by my colleague ctammann to provide a design for the Kria KV260 Vision Starter Kit that would be a power hog for some power testing. Although all of the Kria apps seems to be using a B3136 DPU, I did remember that Xilinx genera...
Introduction
Quick little project to make an egg timer using the MAX II board that I bought over the summer.
Initially, I'll just have it counting down from three minutes. If I feel suitably inspired later, I
might extend it to allow setting t...
Avnet is working on Vitis 2021.1 platforms for several of their hardware platforms.Thanks to this work, I was able to port Vitis-AI 1.4 on the following platforms:Ultra96-V2 Development BoardUltraZed-EV SOM (7EV) + FMC Carrier CardUltraZed-EG SOM (3E...
Having used Vivado as a hobbyist for several years now I feel more confident in tackling the inevitable errors, but still often get stuck. Therefore to help others, and my forgetful self in coming months, I thought a quick blog post may be useful. I ...
Recent Advances in Vivado VHDL-2008 Support Previous posts in this blog were made in the 2018-2019 period. Some of the issues presented were an attempt to work around VHDL-2008 support limitations in Vivado at that point in time. Since then, sig...
Our team at Avnet is working on a new design now. As we go through the various review stages, I was reminded of something that every engineer developing a PCB with Xilinx should know. Tip #1 -- Use Xilinx Documentation NavigatorOf course, every ...
Build a big multiplexer by reusing small multiplexers.FPGA designs are (re)usable as components. In this post I'm showing that you can make a 4-input multiplexer by combining several 2-input multiplexers.A 2-input multiplexer is a simple digital ...
You can interrupt the Zynq ARM side with a signal coming out of the FPGA part of the chip. In this post, I test this.The FPGA part has a few blocks that will generate interrupts. In a Jupyter notebook, I'll try to show that they are detected by the p...
IntroductionThis blog post provides details on how to build and execute the new 2020.2 design for the Ultra96-V2 development board with Dual-Camera Mezzanine. {gallery} Ultra96-V2 Dual Camera PhotosUltra96-V2 with Dual Camera MezzanineUltr...
Hello! Looking for a new Xilinx SBC to play with or the best Xilinx Zynq or Zynq UltraScale+ SOM to use in your product? Can't decide what Avnet SOM or SBC is the best fit for your application? Avnet has just published a new Xili...
When you're working on a Vivado Block design, you can add IP.There are 100s of options available. But you will not find a NOT gate, AND gate, ...They are there though, available under the cryptical name Utility Vector Logic and Utility Reduced Logic&...
Introduction: Back then in February when I roadtested the USB104-A7, I had learned to create block designs using MicroBlaze. I found it very interesting but the available online resources were limited, the tutorials were based on the older versions o...
Read this for info only. The project done at the time didn't work. I'm leaving the blog here as a testimonial that things have become easier and more streamlined with the 2.7 release of the example.It works, and can easily be repeated, with Vitis HLS...
Read this for info only. The project done at the time didn't work.
I'm leaving the blog here as a testimonial that things have become easier and more streamlined with the 2.7 release of the example.
It works, and can easily be repeated, with Vi...
Life hack to automate the creation of a project in Vivado. www.youtube.com/watchvideo source: real time capture of script execution on my laptop Many projects have repeatable steps at the setup stage. This script helps to automate this. It ...
The main target for Zynq family FPGAs is: compute systems with hardware acceleration.
It's architecture focuses on being able to stream data efficiently between ARM and FPGA submodules.
The FPGA can then perform manipulations in hardware that tak...
shabaz made a Software Defined Radio (SDR) Experiment Board. One of the components is a digital quadrature oscillator.It's a circuit with 4 PWM outputs that are each 90° shifted.In Shabaz' blog, the oscillator is made with flip-flops, and controlled ...
