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Threads
548 Discussions
Frequently Asked
Sharing vivado projects
Not Answered
over 3 years ago
Vivado and Zynq: TRI-STATE help
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over 3 years ago
i2c bus in zynq
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over 3 years ago
Issue with blk_memory after design & wrapper
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over 3 years ago
How to fix DMA initialization failure?
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over 3 years ago
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Avnet UltraZed-EG PCIe Carrier Card - Golden Constraints
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130
views
2
replies
Latest
14 days ago
by
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Answered
Avnet UltraZed-EG SOM - Trace Delays
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154
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ZCU208 RFSoC Explorer Toolbox Dual AXI DMA Integration & FIL Workflow Limitations with HDL Coder
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27 days ago
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Not Answered
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0
replies
Started
1 month ago
by
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Discussion
Feedback Requested - Brand New SDR
440
views
4
replies
Latest
2 months ago
by
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Not Answered
Microzed Carrier Board Component Question
0
362
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1
reply
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3 months ago
by
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Discussion
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1000
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8
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Latest
5 months ago
by
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Not Answered
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617
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2
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Latest
6 months ago
by
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Suggested Answer
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5021
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9
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6 months ago
by
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Discussion
Help Object detection and tracking with color space conversion and morph operators
466
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6 months ago
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Discussion
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2530
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Suggested Answer
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1305
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8 months ago
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Not Answered
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1244
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9
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8 months ago
by
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Discussion
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524
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0
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9 months ago
by
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Discussion
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10 months ago
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Suggested Answer
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Discussion
Affordable Versal parts and their penetration in hobbyist circles
2765
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15
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11 months ago
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Discussion
(solved) Did you manage to debug a Microblaze RISC-V with Vitis Unified IDE (2024.1) ?
2417
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5
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Latest
11 months ago
by
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Discussion
Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): solve xsdb segmentation fault
1166
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1
reply
Latest
11 months ago
by
bidrohini
Discussion
Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): connect to the USB debugger as a normal user
433
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0
replies
Started
11 months ago
by
Jan Cumps
>
