Hello,
I have been using the HMCAD 1511 in both ramp test mode and user mode for single channel configuration at a sample rate of 1 Gsps. Describing what sometimes happens in ramp test mode may however better explain my problem.
For ramp mode my spi sequence is as follows:
- Reset ADC using external reset line for 50 ns;
- Initiate Power Down X"0F0200";
- Configure ADC, single mode, clock division by 1, X"310001";
- Select single test pattern, X"250010";
- Specify alternating 1’s and 0’s as test pattern, X"26AA00";
- Power up ADC, X"0F0000";
- Set up FPGA using above pattern;
- Go into user mode, X"250000";
- Switch on the four adcs in the HMAC1511; in the case of the evaluation board that would be X"3A0202" and X"3B0202."
The problem which manifests itself is that when the 4 ADCs are switched on (i.e. X"3A0202" and X"3B0202") eight different test patterns may appear (not always though as sometimes the desired single test pattern may result). When just one ADC is used (for example X"3A0002") a single test pattern will always appear. The figure below illustrates the eight pattern phenomenon.
As can be seen in the attached figure, the performance is completely deterministic. A given byte, x, on the eight channels, will increment to x + 1 (representing an increment of the lower nibble), following the next 7 outputs for a single channel mode operation. Those next seven outputs show that the upper nibble is incrementing by 0x2.
Could someone suggest a reason for this behaviour? Thanks in advance for all of your help.
Arnel Collins
