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Questions about the AVNET Network FMC Module

jb-ch

Hello,

 

I am Jean-Baptiste and I am currently working on ip designs for Ethernet based network. I currently have a setup with a Netpga CML card on which is plugged the Avnet Network FMC module.

https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-fmc-netw1-g-3074457345635205181/

 

The entire design is pure VHDL thus there is no SW part.

The vadj is set to 1.8V and the power led on the network FMC module shows that vadj value on the dedicated leds.

I am able to properly use part of the board but I do have some issues using this setup.

 

1) I am running the same MDC/MDIO configuration on port 1 and port 2 of the Avnet Network FMC. Only Port 1 is up and running (I can see Ethernet traffic with wire-shark). However, the second port remains inactive and the activity leds are not showing anything (doesn't matter the applied speed 10/100/1000 Mbit/s).

2) The users leds on the boards are not very bright, it seems that there is not enough intensity in the applied power signal.

 

Is anyone has experimented some similar issue using this avnet ethernet fmc module?

(Note that I have tried to remove Q1 as described in the Erratum but it doesn't fix my issue with port 2).

 

Many thanks,

Best regards,

Jean-Baptiste

Parents

  • Hello Joshua,

     

    Yes, the constraint file is properly defined according to:

    - NetFPGA-1G-CMLTM Board Reference Manual

    - Network FMC User Guide (v1.0)

    - For the constraint file itself, I used the file AES-FMC-NETW1-G-XDC-File.xdc (from AVNET website) as baseline.

     

    Maybe more infos:

    - I am using a VADJ of 1.8V, I am applying it without doing the procedure of IPMI Identification I2C EEPROM.

    - For each network FMC port (1 and 2) I am using all TX/RX Data, Clock and Ctrl pins as well as the MDC/MDIO ports for configuration.

    - I am using all User LED ports (on the network fmc) as out signal in the constraints file,

    - I am NOT using FMC_PRSNT_M2C_N, FMC_SCLX, FMC_SDAX, M2C_125MHZ_EN, M2C_125MHZ_SEL which is useless in my setup.

     

    The whole system works prepoerly for Port 1, only Port 2 is not working with exact same Configuration and VHDL design.

    Maybe I will have to try with another board to see if the issue is not coming from the netfpga CML as FMC carrier.

     

    Thanks you,

    Best regards,

    JB Ch

Reply

  • Hello Joshua,

     

    Yes, the constraint file is properly defined according to:

    - NetFPGA-1G-CMLTM Board Reference Manual

    - Network FMC User Guide (v1.0)

    - For the constraint file itself, I used the file AES-FMC-NETW1-G-XDC-File.xdc (from AVNET website) as baseline.

     

    Maybe more infos:

    - I am using a VADJ of 1.8V, I am applying it without doing the procedure of IPMI Identification I2C EEPROM.

    - For each network FMC port (1 and 2) I am using all TX/RX Data, Clock and Ctrl pins as well as the MDC/MDIO ports for configuration.

    - I am using all User LED ports (on the network fmc) as out signal in the constraints file,

    - I am NOT using FMC_PRSNT_M2C_N, FMC_SCLX, FMC_SDAX, M2C_125MHZ_EN, M2C_125MHZ_SEL which is useless in my setup.

     

    The whole system works prepoerly for Port 1, only Port 2 is not working with exact same Configuration and VHDL design.

    Maybe I will have to try with another board to see if the issue is not coming from the netfpga CML as FMC carrier.

     

    Thanks you,

    Best regards,

    JB Ch

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