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Digilent Arty Z7 and Reset

14rhb

I would be grateful for some help or a pointer at least to what my issue might be on this problem. To compound the issue I am not very good at articulating the issue in the proper 'Vivado' language and also the development is taking place on another machine, hence the lack of screenshots unless asked for.

 

 

image In the past I have built some designs using the Arty S7-50 and can drag a reset across from the board file and into the block design, everything connects well and I'm image

 

 

image I'm now using the Arty Z7-50 and I am experimenting with ideas and designs. Although this board physically has two reset buttons neither is listed on the board file that can be dragged into the design. I tried to make my own board.xml from the existing one but never managed to get it to be accepted by Vivado.

 

When I make a Microblaze design with the Arty-Z7 the Clock Wizard and Processor System Reset gets added automatically and finally I end up with a reset called reset_rtl_0 being produced. Unfortunately as reset_rtl_0 doesn't exist in the XDC constraints file the build process fails with LOC error citing the reset_rtl_0. I tried adding it to my XDC file using the schematic to identify the reset(s) and tried both pins D9 (CK_RST) and C7 (POR-B) which are both in bank 500. The build complains about this with "Cannot set LOC property of ports. Site location is not valid".

 

## reset button
set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get ports {reset_rtl_0} ];

 

I then also tried to configure using the elaborated design and the I/O ports tab. Neither D9 or C7 are options and I am unable to specify a bank for the reset_rtl_0.

 

Work Around

I have used one of the slide switches to implement a reset to these IP blocks but it seems a bit wasteful when I've only got two on this board to start with !

 

 

Does anyone have any better recommendations or help with this please? Thank you.

  • Hello,

     

    A better place to ask this question is the Digilent user forums:https://forum.digilentinc.com/forum/4-fpga/

     

    That said, I can offer this:  The POR-B and CK_RST signals are both I/Os that are connected to the Zynq PS muxed I/O (MIO).  This limits their use.  Unless you are also using the Zynq processing system (PS), these signals may not be useable (routable to the PL) as a reset for MicroBlaze in the PL.  You may instead want to constrain one of the push buttons BTN[0:3] for the MicroBlaze reset input.

     

    --Tom

  • in reply to narrucmot

    Thanks Tom. We think alike as I did indeed try the Digilent Forum first, but without any comments to my post after a few days and wanting to push on with my project, I decided to post here as I've always find the Element14 community more active...you post proving that theory image.

     

    Your paragraph helps explain and confirm to me the inner workings and why the resets aren't easy to use. I also note when I added a Zynq IP block the resets were taken care of. Looks like I'll be using a button after all to keep things progressing.

     

    Thanks again !