I've spent a while trying to clear an error in a Vivado design and having found the solution online I thought I'd repeat it in E14 for easy reference.
My project is still attempting to use the Digilent ZMOD DAC unit and associated IP as detailed previously in and my current experimental design is shown below:
The error that was baffling me was "the design is empty":
[Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.
After much changing of settings, search various internet articles I found a great explanation from scottyengr on another forum who said:
Since your design only has inputs, the synthesis tool can optimize it to be nothing. In other words without any output, there is no logic needed. The synthesis tool is only going to keep logic needed to produce outputs.
Yep....looking at my design that now makes perfect sense 
[thanks scottyengr]
