I figure johnbeetem will like this talk from 32c3 yesterday:
A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs
https://www.youtube.com/watch?v=9rYiGDDUIzg
A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAsYosys (Yosys Open Synthesis Suite) is an Open Source Verilog synthesis and verification tool.Project IceStorm aims at reverse engineering and documenting the bit-stream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bit-stream files, including a tool that converts iCE40 bit-stream files into behavioral Verilog. Currently the bitstream format for iCE40 HX1K and HX8K is fully documented and supported by the tools.Arachne-PNR is an Open Source place&route tool for iCE40 FPGAs based on the databases provided by Project IceStorm. It converts BLIF files into an ASCII file format that can be turned into a bit-stream by IceStorm tools.This three projects together implement a complete open source tool-chain for iCE40 FPGAs. It is available now and it is feature complete (with the exception of timing analysis, which is work in progress). Speaker: Clifford EventID: 7139 Event: 32th Chaos Communication Congress [32c3] of the Chaos Computer Club [CCC] Location: Congress Centrum Hamburg (CCH); Am Dammtor; Marseiller Stra e; 20355 Hamburg; Germany Language: english Begin: Sun, 12/27/2015 16:00:00 +01:00 License: CC-byHelp us caption & translate this video!http://amara.org/v/HbCf/
cheers,
drew
