Lattice Semiconductor today announced the immediate availability of the Broadcom HiGig MAC IP core for its ECP3 FPGA family. Multiple individual devices interconnected via the HiGig protocol operate as one logical network, providing features like quality of service (QoS), mirroring and link aggregation. The HiGig MAC ensures that the Media Access rules specified in the 802.3ae IEEE standard and HiGig Protocol definitions are met while transmitting a frame of data over Ethernet.
Compliant with Broadcom HiGig and HiGig2 protocol definitions, the HiGig MAC IP core has a 64-bit wide internal data path operating at a maximum frequency of 156 MHz on the Lattice ECP3 FPGA. The core provides XGMII and XAUI interfaces to the PHY layer and supports variable-sized packet transmission with fixed-sized messaging capability (HiGig2 only). With multicast address filtering and 16-bit statistics counters, the core requires approximately 4100 FPGA look-up tables (LUTs) for HiGig implementations and approximately 4700 FPGA LUTs for HiGig2 implementations.
With this new IP core designers will be able to implement lower cost network solutions using Broadcom devices.