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Sanity check for very first FPGA circuit design

r2kordmaa

Hi

 

I have played around with couple of Spartan3 FPGA boards, but have never designed a FPGA circuit before

so here goes small step for mankind, giant leap for me

 

I designed my circuit around SC3S200A(Spartan3A), in a 100pin QFN package

I have done my best, but without prior experience in FPGA circuit design, that might not be enough,

any problems in secondary subsciruits i can deal with, but if FPGA fails to run i have waisted substantial sum on PCB and components

I would rather like to avoid that

 

So would anyone with experience on designing Spartan3(A) circuits be willing to take a look at my design and tell me if the design has any chance of working?

I have attached the schematic PDF

 

Primary consern is page 2, JTAG and boot configuration.

 

FPGA power is on page 3 and IO banks on page1, but i think its unlikely there are problems on these pages that might brick my design

 

Rest of the circuitry is mostly unrelated to FPGA and if some of that doesnt work, its not a huge problem

 

thank you in advance

Attachments:
imageXC3S200A SCH.pdf
Parents

  • Hi!

     

    I don't blame you for being nervous about your first Xilinx design.  If you don't get the configuration right, the symptom is pretty much "nothing works" and it's pretty hard to narrow the problem down.

     

    I took a look at the configuaration connections and it looks like you've faithfully copied the recommended connections from Xilinx UG332 "Spartan-3 Generation Configuration User Guide" Figure 3-2 (in v1.6, Oct 2009).  But I could have missed something so "no warranty is expressed or implied".  I didn't examine other FPGA connections.

     

    I have a few minor suggestions:

     

    1) I see you have series resistors for the JTAG TMS, TDI, and TCK.  That's good, especially for TCK so if there's any ringing you'll be able to damp it using a larger R54.  The resistors on TMS and TDI protect you in case you plug the JTAG cable in backwards, though since they're inputs you're safe anyway.  OTOH, if you plug the cable in backwards VCC is directly connected to your JTAG pod's TMS which could damage it.  I usually connect +3.3V through a 100 Ohm resistor.  You could also add a seventh pin to the header and break it off to make a keyed header.

     

    The XC3S200A has internal pull-ups for the JTAG signals, which is good so you don't get surprises when the JTAG cable is connected.  I like to put an extra 4.7K pull-up on TCK to be sure.

     

    By default, I think the SX3S200A pulls up the JTAG signals after configuration is complete.  Be sure that default is still selected.

     

    2) MODE0-2 have internal pull-ups during configuration, so you really don't need to pull them up to 3.3V to select JTAG.  OTOH, it's nice to have a well-defined input on those for after configuration, though there is an option to have the pull-ups remain after config.

     

    3) Be sure to have a probable test point for INIT_B.  It indicates CRC errors and configuration progress.  INIT_B does have an internal P/U during config, but make sure the internal P/U persists after config or supply an external 4.7K P/U.

     

    4) I personally prefer active-low LEDs to active-high since NFETs are more efficient than PFETs.  So I use a RED LED for "not DONE" instead of a green LED for "DONE".  The "not DONE" LED lights up when the board first comes up and turns off when configuration succeeds.  Answer Record #9819 at xilinx.com says that a Spartan-3A dedicated pin can sink 8 mA, which is enough to provide the 3-5 mA needed to light a modern LED.  If you use the active-high DONE LED, be sure to set the bitstream generator option to drive DONE, which is by default open-drain.

     

    5) When using JTAG mode, be sure you select the JTAG startup clock option when building the bitstream.  This is easy to forget and really frustrating if you don't know about it.

     

    Have fun!  I hope it goes well.

Reply

  • Hi!

     

    I don't blame you for being nervous about your first Xilinx design.  If you don't get the configuration right, the symptom is pretty much "nothing works" and it's pretty hard to narrow the problem down.

     

    I took a look at the configuaration connections and it looks like you've faithfully copied the recommended connections from Xilinx UG332 "Spartan-3 Generation Configuration User Guide" Figure 3-2 (in v1.6, Oct 2009).  But I could have missed something so "no warranty is expressed or implied".  I didn't examine other FPGA connections.

     

    I have a few minor suggestions:

     

    1) I see you have series resistors for the JTAG TMS, TDI, and TCK.  That's good, especially for TCK so if there's any ringing you'll be able to damp it using a larger R54.  The resistors on TMS and TDI protect you in case you plug the JTAG cable in backwards, though since they're inputs you're safe anyway.  OTOH, if you plug the cable in backwards VCC is directly connected to your JTAG pod's TMS which could damage it.  I usually connect +3.3V through a 100 Ohm resistor.  You could also add a seventh pin to the header and break it off to make a keyed header.

     

    The XC3S200A has internal pull-ups for the JTAG signals, which is good so you don't get surprises when the JTAG cable is connected.  I like to put an extra 4.7K pull-up on TCK to be sure.

     

    By default, I think the SX3S200A pulls up the JTAG signals after configuration is complete.  Be sure that default is still selected.

     

    2) MODE0-2 have internal pull-ups during configuration, so you really don't need to pull them up to 3.3V to select JTAG.  OTOH, it's nice to have a well-defined input on those for after configuration, though there is an option to have the pull-ups remain after config.

     

    3) Be sure to have a probable test point for INIT_B.  It indicates CRC errors and configuration progress.  INIT_B does have an internal P/U during config, but make sure the internal P/U persists after config or supply an external 4.7K P/U.

     

    4) I personally prefer active-low LEDs to active-high since NFETs are more efficient than PFETs.  So I use a RED LED for "not DONE" instead of a green LED for "DONE".  The "not DONE" LED lights up when the board first comes up and turns off when configuration succeeds.  Answer Record #9819 at xilinx.com says that a Spartan-3A dedicated pin can sink 8 mA, which is enough to provide the 3-5 mA needed to light a modern LED.  If you use the active-high DONE LED, be sure to set the bitstream generator option to drive DONE, which is by default open-drain.

     

    5) When using JTAG mode, be sure you select the JTAG startup clock option when building the bitstream.  This is easy to forget and really frustrating if you don't know about it.

     

    Have fun!  I hope it goes well.

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