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FPGA - Let’s make it LOGical …

Former Member

Hi There FPGA Group!


This is Mike and Jonathan of ValentF(x).  We would like to introduce ourselves as FPGA enthusiast and makers that want to see FPGAs used more and are glad that element14 has the same goal.  We see FPGAs a game changer, especially when used with low cost, highly supported CPUs like the BealgeBone and Raspberry Pi.  We have been hard at it trying to come up with a solution that allows users an easier way of working with FPGAs and think we have a good start with the LOGI development boards.  We certainly don’t have the perfect solution, but hope we have a start to what we hope continues to evolve into what users want and need to use them.  In order to be make it better and let evolve we NEED your feedback and input! Don’t be shy about telling us what you would like to see when working with FPGAs, especially when conjoining it with a CPU!


Community involvement@

We hope to get involved on the element14 community with respect to working with FPGAs.  We see the potential for endless projects using CPU/FPGA, interesting discussions about how FPGAs can complement CPUs, etc.  What kind of a material or content would you like to see regarding the use of FPGAs?  Here are some of our thoughts.


  • Create FPGA related blogs that are practical and project based that focus on FPGA topics and projects involving the use of FPGAs.
  • Google hangouts for questions for users to talk FPGAs, show and tell their FPGA projects
  • Collaborative projects - We really just want to have fun creating cool stuff with FPGAs.  It is even funner and more We have some based projects that we have created that we would love for others to get involved in with LOGI face and LOGI UGV.

Your thoughts and suggestions!

We hope to get any feedback from you relative things we can do to help, what we can do to better the LOGI boards and anything else you want to let us know!


Let's start talking!



  • I'm glad to see that you have a good distributor for the LOGI boards.  I've been watching LOGI develop for almost two years now from when they were first discussed at the RasPi forum and here at element14 with various Maker Faire demos.  I'm looking forward to playing with one.

     

    I took a look at the ValentF(x) Wiki and there's an inconsistency between the block diagrams and component identification drawings in the LOGI-Pi and LOGI-Bone Quick Start Guides and User Guides.  Specifically, the SDRAM is not labeled as such in the User Guides.  I think the Quick Start Guides are (more) correct.  I'll let you know if I find other issues once I start playing with a board.

     

    Thank you for posting the schematics.  One thing you might consider for a future version:  When I design a Xilinx FPGA board, I like to use a red "not Done" LED instead of the green Done LED you use.  That way when you turn on the board, you get a big nasty red indication that the FPGA is not programmed.  You also get that indication if anything happens that un-programs the FPGA, such as accidentally shorting Prog to ground with a probe.  The red "not Done" LED makes a nice pull-up for the Done pin.  When you program the FPGA correctly, the "not Done" LED goes out.  This also saves a bit of power, since in normal operation the LED is off.  JMO/YMMV

  • Former Member
    Former Member in reply to johnbeetem

    Hi John,

     

    Thank you for your long-term support!  Indeed it has been a long and learning road from the days of FPGA Mark1 and getting feedback from MakerFaires 2012/13!  We have certainly recieved a great deal of valuable feedback from supportive users such as yourself and look forward to continue to receive and improve and hopefully have a heck of a time in the process!

     

    Thanks for the feedback on the wiki.  I will head over and fix it up direclty.  I imagine this is not the only "bug" in the docs as we have been changing and evolving, so please let us know as you see issues!

     

    Good idea with the NOT Done programming function! This is a nice solution based upon the Done pin being configured, by default, as an open drain.  Coincidentally the open drain configuration does serve for a very very low current source for the current Done LED after configuration, which very very dimly lights upon configuration. But, I like your inverted solution.  We are working on a couple of other "programming features" that we hope to add to future boards as well.

     

    Maybe a LOGI requestion dicussion thread would be nice for these types of of suggestions and further brainstorming.

     

    Looking forward to your hands on feedback!

     

    Cheers!