Barriers to designing with FPGAs?

I feel that FPGAs are a solution seeking a problem to a certain extent.  It is a law of commodities that the first sip has the greatest worth.  Making them bigger and bigger when they are already really big doesn't seem to make them much more useful.  They would be fun if there wasn't the barrier of the software.  IRL, for most common problems, they are just too much.  They are marketed in a turgid manner; show me useful apps, not teabag me with fun fax about how this year's model is 4x more capacious than last year's model.  Just after they first came out I plunked a half K for an entry-level programmer (I was willing to do the high-level programming on graph paper and xeroxes from the databook with a pencil) for replacing jellybeans.  Lattice changed their chip, my programmer was now worthless.  Xeltek told me to cheer up and send them a further K!  This really soured me on the idea that these cats would do a small fry such as myself any justice.  The eeprom-based units of today obviate the need for a unique programmer, but seems to do nothing for the bureaucracies that decide that they really don't care about us.  Then after years and years these factors wonder why they have been unable to develop a user community!

I was at a dinner party recently with a woman who has worked for decades for a major e- distributor.  She insisted that most sales are to govt's and institutions, major corporations, commodity parts.  Their interest in things like dev boards and the 'make' community they saw as something to entertain themselves while they waited for Hitachi's check to arrive for that last truckload of electrolytic capacitors.

Hers is the largest corporation in Arizona.  There is no way they care about your hundred-dollar one-off dev board in any real, economic sense.  Their attitude is 'good luck, smartie!'

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Also if your logic needs are combinatorial rather than sequential, and your number of inputs is similar to your number of outputs, you can use some kind of ROM as an LUT, as an alternative.

Xilinx Wepack usage

Webpack ise is free to use for small to mid-grade chips.  The high end chips require a full license.  See the webpack software matrix can be found here, which shows any limitations to the webpack vs full versions.

Webpack is free to use commercially.  Here is a discussion where Xilinx’s motives are stated.

Altera also has a quartus web edition that is free to use and it appears to have the same un-limited structure until using large devices.  See the comparison chart here.

Though, it is free, it is bulky and not open.  John B. has started a great project which is moving in the right direction to opening things up to open tools. 

Programming requirements of Xilinx FPGAs - no expensive programmers needed

Xilinx and Altera chips offer a very basic way to load the configuration files (bit streams) using a slave serial data stream.  The LOGI boards use the Raspberry Pi or Beaglebone to simply load a bitstream dynamically.  This makes it nice to dynamically have full control of a single bitstream or multiple bit streams being loaded based on changing needs of the system.  I see the Rpi or BBB as a very low cost programmer + very powerful coprocessor.

Alternatively there are some relatively low cost programmers from digilent inc (~$50)  that can be used interface with the FPGA using JTAG.

Xilinx Wepack usage

Webpack ise is free to use for small to mid-grade chips.  The high end chips require a full license.  See the webpack software matrix can be found here, which shows any limitations to the webpack vs full versions.

Webpack is free to use commercially.  Here is a discussion where Xilinx’s motives are stated.

Altera also has a quartus web edition that is free to use and it appears to have the same un-limited structure until using large devices.  See the comparison chart here.

Though, it is free, it is bulky and not open.  John B. has started a great project which is moving in the right direction to opening things up to open tools. 

Programming requirements of Xilinx FPGAs - no expensive programmers needed

Xilinx and Altera chips offer a very basic way to load the configuration files (bit streams) using a slave serial data stream.  The LOGI boards use the Raspberry Pi or Beaglebone to simply load a bitstream dynamically.  This makes it nice to dynamically have full control of a single bitstream or multiple bit streams being loaded based on changing needs of the system.  I see the Rpi or BBB as a very low cost programmer + very powerful coprocessor.

Alternatively there are some relatively low cost programmers from digilent inc (~$50)  that can be used interface with the FPGA using JTAG.