Barriers to designing with FPGAs?

Hi,

This is a very interesting question.   With ValentFX we try to smoothen the learning curve for existing micro-controller/micro-processor users to begin to use FPGAs.

One simple solution that we are pursuing is an online system-level edition of FPGA architecture (www.valentfx.com/skeleton). The user can create a hardware architecture using existing open-source IP (hardware components) represented by grapical components and then generate the corresponding top-level architecture and project for Xilinx ISE. For Linux users, the tool also generates a Makefile that can call Xilinx tools with no need to open the Xilinx ISE GUI.

While this is not enough for someone to learn to design hardware, it is one way to get non-hdl developers  started doing things before they need to learn all the associated concepts of digital hardware design.

Because we want our users to get their hands dirty and learn to write HDL we have started to experiment with alternative languages for HDL. The result of our experiments will be in a blog post we plan to post soon (sometime next week). We tested PSHDL and MyHDL that propose two different approaches for hardware design and they both work very well. The only thing is that i'am still not convinced that they are entry-level languages because they require to master quite a lot of concepts (especially MyHDL). I personally use VHDL and when testing those language i tend to map the VHDL construct to the MyHDL/PSHDL languages, and i would be interested to get beginners’ feedback on these or other languages. Testing those tools allowed us to define a proposed HDL language with the features one might expect and be comfortable with for a language to begin developing HDL.

Proposed HDL Language Attributes

- Based on well adopted syntax so users can takes advantage of existing editors features (auto-completion, syntax highlighting, ...)

- Remove as much syntactical noise as possible. The user should not have to explicitly define what can be inferred from its constructions

- User should be able to write a basic example in just a few lines and clicks (three clicks should be enough to run a small example)

- An architecture can be defined in a single file (ease sharing) and with no need to define a complicated project structure (Arduino does this really well for micro-controllers)

- Should be vendor agnostic …

What features would you expect from a entry-level HDL Language?

Regards,

Jonathan Piat

CTO of ValentFX, Co-Counder of the LOGI-Boards

Hi,

This is a very interesting question.   With ValentFX we try to smoothen the learning curve for existing micro-controller/micro-processor users to begin to use FPGAs.

One simple solution that we are pursuing is an online system-level edition of FPGA architecture (www.valentfx.com/skeleton). The user can create a hardware architecture using existing open-source IP (hardware components) represented by grapical components and then generate the corresponding top-level architecture and project for Xilinx ISE. For Linux users, the tool also generates a Makefile that can call Xilinx tools with no need to open the Xilinx ISE GUI.

While this is not enough for someone to learn to design hardware, it is one way to get non-hdl developers  started doing things before they need to learn all the associated concepts of digital hardware design.

Because we want our users to get their hands dirty and learn to write HDL we have started to experiment with alternative languages for HDL. The result of our experiments will be in a blog post we plan to post soon (sometime next week). We tested PSHDL and MyHDL that propose two different approaches for hardware design and they both work very well. The only thing is that i'am still not convinced that they are entry-level languages because they require to master quite a lot of concepts (especially MyHDL). I personally use VHDL and when testing those language i tend to map the VHDL construct to the MyHDL/PSHDL languages, and i would be interested to get beginners’ feedback on these or other languages. Testing those tools allowed us to define a proposed HDL language with the features one might expect and be comfortable with for a language to begin developing HDL.

Proposed HDL Language Attributes

- Based on well adopted syntax so users can takes advantage of existing editors features (auto-completion, syntax highlighting, ...)

- Remove as much syntactical noise as possible. The user should not have to explicitly define what can be inferred from its constructions

- User should be able to write a basic example in just a few lines and clicks (three clicks should be enough to run a small example)

- An architecture can be defined in a single file (ease sharing) and with no need to define a complicated project structure (Arduino does this really well for micro-controllers)

- Should be vendor agnostic …

What features would you expect from a entry-level HDL Language?

Regards,

Jonathan Piat

CTO of ValentFX, Co-Counder of the LOGI-Boards