Thoughts on interesting FPGA modules?

I'm still looking for a cheap FPGA that has PCI Express on chip.  I only need PCIe 1.1 (2.5 Gb/s full duplex), and even with that I don't need the bandwidth -- I just need the connectivity.  Xilinx Spartan-6 has PCIe, but the smallest chip is the LX25T.

You can (or could) get a PCIe 1.1 transceiver from NXP, but it had a byte-wide interface which is 250 MB/s, pushing FPGA limits.  The on-chip PCIe typically have 32 bit interfaces, so you can work at 62.5 MHz which is a lot more manageable.  It's also a PITA to have to do CRC calculations using block RAM when they're so easy to do with dedicated hardware.

This is a future application.  I currently have a very nice design for a customer that uses a small fraction of a 33MHz 32-bit PCI interface.  It works fine, but it's getting harder to find CPUs (SoCs) that have PCI.  So at some point I expect to need PCIe, assuming that customer continues that product line   It's also something I'd like in my "bag of tricks".

From what I can tell, the Spartan-6 LX has LVDS pins but they don't have clock/data recovery so it only works for standards like HDMI that have a separate clock.  I think you have to go with the LXT to get CDR, at least at high speed.  Is this impression correct?

Hi,

i tried clock recovery on LX9, and even if you can create a serial receiver with phase detector (won't do clock recovery, but if you have a local clock at bus frequency, you can at least recover the phase of incoming data) using XIlinx IP Core (SelectIO) it won't synthesize on LX9. I haven't tried to synthesize on LXT variant.

Lattice has some nice (cheap) dev board with PCIe capabilities (ECP3), and a cool promotional video : Lattice ECP3 FPGA Jamz - YouTube

Hi John,

It sounds like you are getting into some fun stuff.  This is what I love about FPGAs in that you can really delve into some interesting topics and mix and match to create unique applications that are not available on most processors.  What I would like to see is the usage of the LX9 capabilities including the LVDS, with the spec of 950Mbps, there are some pretty fun applictions beyond single ended signalling that can be explored.  We are hoping to interface with interesting source syncronous LVDS sensors and do some interesting things.  I think this would be a nice prelude into delving into the more advance LVDS protocols that implement CDR.

Indeed the LX9 does not have dedicated CDR, but I have seen some interesting topics talking about "soft" implementations and some other approaches including, aligned lock loop (ALL), which I have not seen much mention of lately.  Here is an oldie but goodie article that talks about ALL and the sequence of technology progressing up to the need of CDR from older transceiver impelementations.  It might be useful for others who come along this discussion to see the progression.

Hamster has done some interesting low cost LVDS links and deal with the hair pulling timing issues with floor planning with some a great write-up here High Speed Link - Hamsterworks Wiki!

Once one has pulled out enough hair and understood the concepts they can really appreciate CDR and the amazing protocols available that are based upon it.

Have you looked at these chips for GTP/CDR?  The smallest ECP3 with PCIe seems a little weak for the price (single channlel - $31 single qty) and the LXT25 seems kind of expensive for the functions (2 channel - $55 single QTY) I like the looks of the  Artix7-35T (4 channel - $37 single QTY), Note that it appears that the Artix7-15T (lower cost and 4 GTP's) will be available soon and should be a much better price than the 35T,  or possibly the new Max10 or cyclone?  I like the price on the new Max10 dev boards and glad to see they left us with a TQFP-144 package!

Cheers,

Mike

Michael Jones wrote:

 

Indeed the LX9 does not have dedicated CDR, but I have seen some interesting topics talking about "soft" implementations and some other approaches including ALL (which I have not seen much mention of lately).  Here is an oldie but goodie article that talks about ALL and the sequence of technology progressing up to the need of needing CDR from older traceiver impelementations.  It might be useful for others who come along this discussion.

Thank you for the Align Lock Loop (ALL) reference.  I'll have to take a closer look at it when I have a chance.  Max's article looks like a good survey of the various techniques.  I wonder why ALL hasn't caught on?  Is there a technical problem, or is it just that it's not practical until a bunch of chips start adopting it?  Or maybe IBM's patents hadn't expired yet?  Maybe I'll ask Max for an update after I've slogged through the article.

Yes, it would be great to hear an update!