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Project IceStorm: fully open-source FPGA tools for Lattice iCE40

johnbeetem

As some of you may have noticed, I've been obsessed for many decades with having open FPGA bitstream documentation so that people can write their own FPGA designs tools, especially FLOSS (Free-as-in-Liberty Open Source Software).

 

I recently found out about IceStorm, a project that has somehow reverse-engineered and documented the Lattice iCE40 FPGA.  They've actually put together a fully-open-source tool chain with Yosys for Verilog synthesis and Arachne_pnr for placement and routing.  I don't know how usable or robust the tools are.  I'm planning on taking a close look starting next month.

 

If you're interested, here's the IceStorm link, which has links to the other tools: Project IceStorm

Discussion of Yosys and the tools is at reddit: Yosys Open SYnthesis Suite

 

Update: Here are a couple of nice Hackaday items about IceStorm:

 

From 29 March 2015: Reverse Engineering Lattice’s iCE40 FPGA Bitstream | Hackaday

From 29 May 2015: An Open Source Toolchain For iCE40 FPGAs | Hackaday

 

Update 2: Here are some good IceStorm installation instructions: Projet IceStorm : le FPGA libéré ! | Front de Libération des FPGA.  They're in a combination of French and GNU/Linux.

 

Here's the Lattice IceStick directly supported by IceStorm: Lattice Semiconductor: ICE40HX1K-STICK-EVN iCEstick Evaluation Kit.  It's US$20.89 in the USA.

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  • Hi John,

     

    Having worked in the bit-slice world I understand your interest in FPGA devices.

    Just having access to the raw power of the silicon to solve problems is definitely addicting.

     

    Alas, I can no longer handle the detail needed to put this level of implementation to good use.

     

    Do you have any projects planned or are you just getting the tools ready to use?

     

    DAB

  • in reply to DAB

    DAB wrote:

     

    Do you have any projects planned or are you just getting the tools ready to use?

    I'm planning to incorporate IceStorm and arachne-pnr into my XXICC (21st Century Co-design) software.  This will provide an alternate open-source design flow, with designs specified using my GCHD (GalaxC for Hardware Design) text language and/or logic diagrams instead of Verilog or VHDL.  GCHD is IMO a much cleaner language and lends itself better to synthesis than Verilog and VHDL, which are designed primarily for simulation.  For IceStorm, XXICC will synthesize GCHD into BLIF (Berkeley Logic Interchange Format), the input format for arachne-pnr.  The output of arachne-pnr is a text file for IceStorm, which generates the Lattice bitstream.  XXICC doesn't need the Verilog step.

     

    I actually have a proof-of-concept version working with Boolean-only designs.  I can go from GCHD to a running example in a couple seconds, much faster than Lattice tools.  I'd like to make some major improvements to my GCHD (GalaxC for Hardware Design) implementation before the next XXICC release.  Unfortunately, I've had too many other demands on my time to work on XXICC these days so I don't know when I'll be able to get back to all this goodness.

     

    I don't have any specific hardware projects at this time.  My goal is to make FPGAs fun and easy.  They're very hard with vendor FPGA tools, and it's really held the technology back from its potential.  The yosys - arachne - IceStorm chain is a lot better, but I think XXICC will be even better... and more fun!

  • in reply to johnbeetem

         Just a wondering how are things on the FPGA front.

    Thanks,

    Clem

  • in reply to clem57

    Hi Clem,

     

    Thanks for asking!  Unfortunately, I'm currently swamped with family obligations so I've had to put XXICC on the back burner for a while.  It's too bad, since thanks to IceStorm I can now make a very decent FPGA design suite using GCHD and other XXICC tools as the front end, with arachne-pnr and IceStorm as the back end.  I pretty much know what I want to implement when I can get back to XXICC.  I'm also planning ahead some ideas for the future of XXICC.  These are things that are hard to think about when I'm in the middle of an implementation so it may be good that circumstances are forcing me to sit back from implementation for a bit.

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  • in reply to clem57

    Hi Clem,

     

    Thanks for asking!  Unfortunately, I'm currently swamped with family obligations so I've had to put XXICC on the back burner for a while.  It's too bad, since thanks to IceStorm I can now make a very decent FPGA design suite using GCHD and other XXICC tools as the front end, with arachne-pnr and IceStorm as the back end.  I pretty much know what I want to implement when I can get back to XXICC.  I'm also planning ahead some ideas for the future of XXICC.  These are things that are hard to think about when I'm in the middle of an implementation so it may be good that circumstances are forcing me to sit back from implementation for a bit.

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