Elbert V2 - Spartan 3A FPGA Development Board

Question

Does anyone have this same model of card? I need some help , because I 'm trying to implement a counter from 0 to 99. But so far it has not worked for me. It is a sample code I found on the web. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cotador is
 Port ( reloj : in std_logic;
 reset : in std_logic;
 habent : in std_logic;
 habsal : out std_logic;
 cuentamax: in std_logic_vector (3 downto 0);
 selec:in std_logic_vector (3 downto 0);
anodosut std_logic_vector (3 downto 0);
salida : out std_logic_vector (6 downto 0));

end cotador;

architecture Behavioral of cotador is
 signal clock:std_logic; 
 signal count:std_logic_vector (3 downto 0);
 begin

process(reloj)
 variable conta : integer range 0 to 50000000 :=0;
 begin
 if reloj = '1' and reloj'event then
 if conta =50000000 then
conta :=0;
clock <='1';
else
conta:=conta+1;
clock<='0';
end if;
end if;
 end process;

process (cuentamax,clock, reset)
 variable cuenta: std_logic_vector (3 downto 0):="0000";
 begin
 if reset = '1' then
 count<="0000";
 elsif clock='1' and clock'event then
 if habent='0' then 
 if count = cuentamax then
 count<="0000";
 else
 count<=count+1;
 end if;
 end if;
 end if;

if count=cuentamax and habent = '0' and clock = '1' then
 habsal<='0';
 else
 habsal<='1';

end if;

end process;

with count select
salida<="1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"1000000" when others;

anodos<=selec;

end Behavioral;

michaelkellett · Accepted Answer

Hello Pablo,

You are starting out so it's time to get into good habits - don't use IEEE.STD_LOGIC_ARITH.ALL; but use NUMERIC_STD instead - there are very good reasons for this which you can check out on the web.

http://vhdlguru.blogspot.co.uk/2010/03/why-library-numericstd-is-preferred.html

http://www.alteraforum.com/forum/showthread.php?t=20925

There are many more references to be looked at if you like.

John has explained some of the issues in the code - if cuentmax is input on pins nothing will happen unless it's set up. And as John has pointed out it will never count to 99.

So - how have you tested it and what did you see.

(There are other bad things in this design as well - clocking a process from the output of another process will often cause timing issues. Processes should ALWAYS have names - so we can refer to them easily !)

And most importantly - how are simulating it.

Simulation is the key to FPGA development - you will never get anything complex to work unless you learn how to do simulation.

The Xilinx tools will include a simulator.

MK

johnbeetem · Answer

I don't have an Elbert V2 and I my FPGA expertise is primarily Verilog, but I'll try to make some general suggestions.

First, numato.com has some tutorials for Elbert V2. Look near the bottom of the Elbert V2 page and click on the Tutorials tab: http://numato.com/elbert-v2-spartan-3a-fpga-development-board.html

I haven't looked at the tutorials myself, but maybe one provides a step-by-step guide to compiling a VHDL design and downloading it. Getting your first FPGA design to download and work is difficult, so I recommend doing it first with a simple working design, preferably from a tutorial that's been tested.

Second, from what I can tell of the example given my limited VHDL, it seems that it can only count up to 10. process(reloj) begins some code to divide by 50 million, which I assume is dividing Elbert's clock oscillator down to 1 Hz so you can watch the counting. process(cuentamax, clock, reset) begins code for a 4-bit counter that increments count from 0 up to (and I think including) cuentamax. salida is a 7-bit vector that displays a 7-segment digit for count.

There doesn't seem to be a main program that sets a value for cuentamax, or maybe you're supposed to input it from the DIP switch.

You need a User Constraint File (UCF) to define the pinout, or you can use the GUI tool in the Xilinx ISE software. Use the Elbert V2 schematic to see which pin numbers are connected to switches, LEDs, and the clock oscillator.

If you're programming the FPGA using JTAG over USB, be sure you set the start-up clock to the JTAG clock in the options for bitstream generation. That's an easy thing to miss.

Hope this helps!

Elbert V2 - Spartan 3A FPGA Development Board

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