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FPGA
Forum Looking for simple FPGA dev board that easily supports 1.8V I/O.
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  • fpga
  • 1.8v
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Looking for simple FPGA dev board that easily supports 1.8V I/O.

chrisindallas
chrisindallas over 8 years ago

Hi, I have a MIPI serial protocol project that needs 1.8V I/O. While I see that many FPGAs support banks of this relatively low voltage, I haven't found a dev board where I can easily select 1.8V with a header or switch. Most have all the banks hard wired to 3.3V. I'd rather find a board with these options in mind than cut traces and route new jumpers to the FPGA since it's possible that I may send these out to customers. Are any of you familiar with dev board with this kind of feature?

 

Thanks,

 

Chris Atkins

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  • chrisindallas
    chrisindallas over 8 years ago in reply to johnbeetem +2
    Hi John, thanks for your reply. The MIPI RFFE protocol I'm using is not differential. In one read sequence, the master writes the command and address information and then releases the data while continuing…
  • johnbeetem
    johnbeetem over 8 years ago +1 suggested
    I did a little looking about, but I didn't find anything. Small boards typically don't have selectable I/O voltage because there's no room for the jumpers and "those frills cost money". You might be able…
  • johnbeetem
    0 johnbeetem over 8 years ago

    I did a little looking about, but I didn't find anything.  Small boards typically don't have selectable I/O voltage because there's no room for the jumpers and "those frills cost money".  You might be able to find it in larger, more expensive boards from the FPGA manufacturers.  You might be better off using an external level converter for prototypes, and then do the right thing if you make a custom board.

     

    I always recommend Joel Williams' Cheap FPGA Development Boards list.

     

    Finding an FPGA board that gives you a MIPI interface may be the bottleneck rather then 1.8V.  It's a differential interface, isn't it?  If so, you might be able to get by with 3.3V differential inputs and use resistor voltage dividers for 3.3V outputs.  For a non-differential signal, you could use a 3.3V differential input and set one side to a voltage divider to give you a threshold.  I think that's what Xilinx Spartan chips do internally, but there's no reason you can't do it externally.  Then use a resistor divider for your outputs and Bob's your uncle.  Some FPGAs have series resistor options for their outputs so you'd only need a pull-down.

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  • chrisindallas
    0 chrisindallas over 8 years ago in reply to johnbeetem

    Hi John, thanks for your reply. The MIPI RFFE protocol I'm using is not differential. In one read sequence, the master writes the command and address information and then releases the data while continuing to supply the clock.

     

    An external level shifter is one way to approach this, but I'd probably have to make a custom level shifter because RFFE uses a bidirectional data pin. Level shifters like the TXB0104 have an OE pin, but it disables the output on both sides of the translator. Something like the SN74AVC4T774 with direction pins might work if I used a separate chip for the data so that OE wouldn't effect the data. Either way, not as elegant as having 1.8V I/O, but it's an option.

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