Connecting Verilog to Synthesis

Question

Hey everyone! Wish I had seen this group earlier.

I'm hoping there's a few here who are familiar with the Xilinx ISE. I'm finally making a concerted effort to learn Verilog and this time around I'm doing well. I'm grasping the language concepts well, and am enjoying the book I picked up from the local University library (public library is a bit short on HDL books!) called "Verilog for Digital Design" written by Frank Vahid and Roman Lysecky. Make sure to check for the 2002 edition, there are older versions as well. This book is the perfect blend of theory and practical code writing.

Anyway, I wanted to try implementing a simple design of my own, essentially recreating the functionality of four 74193 up/down binary counters. The inputs are four buttons, up, down, load and store. The load and store buttons control signals for a later stage of the design.

I wrote the counter module, then created a top level module and instantiated the counter module. I simulated it with a simple test bench and it worked!! Amazing!

However, now I'm trying to implement it in my Spartan-3E FPGA and I'm having trouble figuring out the hierarchy of a typical design. Clearly the top level module interfaces with the actual pins, and then passes these states to the instantiated module. But how do I pick which pins connect to the top level module? I see that PlanAhead seems to implement this stage of the design but I'm confused on how to put it all together. I'm also having trouble connecting the counter module ports to the top level module. It keeps giving me errors for the output bus, saying something like it's not a proper lvalue? The counter module has the counter output declared as an output reg[15:0] ... is that incorrect? The top level module also has the actual output declared as an output reg, is it improper to commect these types together? I figured within the counter module that the output should be a reg ad not a wire, because it needs to hold its value. Plus the output needs to be manipulated directly and it seems a reg was the easiest way to do this

Perhaps these questions will be answered later in the book but the ISE/Xilinx specific problems won't be addressed as the author uses different software and never directly talks about specific brands. He does focus on both simulation and synthesis though, which is what I was looking for. Most books on Verilog place a heavy focus on simulation, and while I've discovered how useful simulation is, I have this Xilinx dev board that I want to play/learn with!

Thanks everyone for reading all that. Will be happy to share more as I learn more. If it helps I can post my code here.

johnbeetem · Accepted Answer

A few things:

1. Since count_Out is declared "reg" in module "counter", the bus it connects to in the root module should be declared as a wire. Otherwise you're going through two regs, at least that's how I understand it.

2. I've never used included "input", "output", and "reg" in a "module" declaration, e.g., module counter(input Clk, input b_Up, input b_Down, input Rst, input OE, output reg[15:0] count_Out); I've always listed the I/Os on separate lines, like the examples at Wikipedia's Verilog page: http://en.wikipedia.org/wiki/Verilog#Example

This is probably because I learned Verilog in 2000 so I pre-date the 2001 and 2005 improvements.

3. From your warnings, it looks like module main's connections to "counter" aren't compatible, so XST is tossing everything away. Make sure the connections are in the correct order and that directions and bus widths are compatible.

4. Follow the correct template for registers. These are cleverly hidden in ISE. In ISE 12.4, go to the Edit menu and select Language Templates. Then click your way down the hierarchy to Synthesis Constructs / Always / Posedge Clocked and ISE shows you the templates for various types of flip-flops and latches, all of which can be multiple bit. For example, here's a positive edge-triggered register with active-high async reset and active-high clock enable:

always @(posedge <clock> or posedge <reset>)

if (<reset>) begin

<signal> <= 0;

end else if (<clock_enable>) begin

<signal> <= <clocked_value>;

end

If you follow this template, XST will recognize that you want that kind of register and generate the correct logic. This is how I design with Verilog: I imagine the logic I want, and then write the code that XST recognizes for generating that logic. It's very much like the early days of C compilers when you could get much better code if you first imagined the assembly language and then wrote code that would help the compiler get there.

In your case, I think your Rst is confusing XST since it's not following the if-then-else structure of the template.

5. There's no need to specify count_Out[15:0] each time. If you say count_Out by itself, it's the whole 16-bit register.

6. If you increment the value of count_Out, you don't need to worry about wrapping the value. Just write count_Out+1 and it will produce a 17-bit value, which if you assign back to count_Out XST will drop the carry out.

7. Now that you have a common clock, here's an easy way to update the up/down counter:

count_Out <= count_Out + b_Up - b_Down;

So now you can do the async reset and counter update like this:

always @(posedge Clk or posedge Rst)

if (Rst) count_Out <= 0;

else count_Out <= count_Out + b_Up - b_Down;

This is a fine example of how Verilog can create compact source code.

johnbeetem · Answer

I've never used PlanAhead. I always use a User Constraint File (.ucf) to define the pinout. The easiest way is to start with a working .ucf as a template, and then modify it. For example, here is the UCF file for the Papilio One FPGA board from Gadget Factory: http://forum.gadgetfactory.net/index.php?/files/file/2-papilio-one-generic-ucf/

Here's a simple 4-bit up-counter:

module UpCounter(Pclk, K);

input Pclk; // 32 MHz Papilio clock.

output [3:0] K; // 4-bit counter;

reg [3:0] K;

always @(posedge Pclk)

K <= K + 1;

endmodule

This is the root module, and the pins Pclk and K[3:0] are the external pins.

Once I have this in a .v file, I create a UCF with the same module name, UpCounter.ucf.

Here are the relevant lines:

NET Pclk LOC="P89" | IOSTANDARD=LVCMOS33 | PERIOD=31.25ns;

NET K<0> LOC="P58" | IOSTANDARD=LVTTL;

NET K<1> LOC="P41" | IOSTANDARD=LVTTL;

NET K<2> LOC="P34" | IOSTANDARD=LVTTL;

NET K<3> LOC="P25" | IOSTANDARD=LVTTL;

I use the notation K<i> to reference bit i of bus K.

I typically use ISE Webpack 12.4, with XST for synthesis.

ISE has a tool for interactively editing the pinout, but I find .ucf quicker since you can use standard text editor copy/paste and replacement operations.

michaelkellett · Answer

@ Alexander - good advice from John - I'm going to add some lateral comments.

I haven't used Xilinx tools for years having moved to Lattice (mainly because I see them as being long term interested in low cost FPGAs and smaller users) - Lattice do have quite a few low cost (and low power) parts in resaonable packages (and some really nice low power parts in difficult-to-use-at-home BGA packages.)

The Lattice toolset includes Aldec HDL with a nice block diagram editor which takes care of all the awful tedium of connecting inputs and outputs of blocks.

Finally - before you invest too much time in Verilog at least take a look at VHDL - I won't say that one is better than the other but I certainly find that VHDL suits my way of working far better than Verilog does. (I think John finds the opposite )

MK

Connecting Verilog to Synthesis

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