GIC vs AXI Interrupt Controller

Good question.  I've thought about this before as well, but this is the first time I've really taken a look into this so I'm not really an expert.  Before reading this, I would suggest skimming through the "IP Facts" section of pg099.

One of the first things to keep in mind, is the resource utilization of the AXI Interrupt Controller.  In it's most complicated configuration, this IP only uses about 500 LUT's and 500 registers which is a very small amount of resources.  So just keep in mind that the IP isn't really doing anything crazy.  Most of its features are simple convenience functions to take full advantage of the GIC.  So if the GIC is a generic interrupt controller, then the AXI Interrupt Controller is a specialized interrupt controller.  In other words, like a device driver, the GIC provides a mechanism, while the AXI Interrupt Controller provides a policy.

The next thing to consider is what the AXI-lite interface is actually doing in the AXI Interrupt Controller.  Like any other IP, the AXI-lite interface allows designers to memory map a device's register space into memory.  This means FPGA designers can reconfigure the IP during runtime.  This is really helpful if you want to use features like the Interrupt Enable Register (IER), which allows you to enable/disable interrupts.  Since the priority between interrupt requests is determined by vector position, there could be situations in which a designer needs to temporarily disable high-priority interrupts to allow low-priority interrupts to meet a deadline.  Or more simply, maybe a designer just wants to be able to poll the status of a register through the ISR/IPR.

Additionally, the AXI Interrupt Controller has other features that can be enabled before runtime.  For instance, there is a fast interrupt mode which uses extra interface signals to pass the address of the interrupt service routine to the processor directly to reduce latency.  There are also features to control bus width, features to cascade AXI Interrupt Controllers, and features to specify input sensitivities.

All in all, from a hardware standpoint, I don't think the AXI Interrupt Controller offers anything groundbreaking, but from a software perspective, I have found some of its features useful.  Having said that, I am glad this IP exists.  If I ever wanted to implement my own controller, Xilinx has provided a good skeleton to do so in both hardware and software.  For instance, maybe instead of using a priority scheme based on vector position, maybe it could be useful to implement a round-robin priority scheme.  Although this may be hard to do from scratch, having the skeleton of the AXI Interrupt Controller suddenly makes the task much easier.

Although I might be mistaken, I believe one other use case is that interrupts in the Vitis Acceleration flow must be connected to an AXI Interrupt Controller in order for the dynamic_postlink.tcl script to work.

All in all, I think connecting interrupts directly to the PS/GIC is a perfectly fine practice, but the AXI Interface Controller offers a little more flexibility especially when dealing with lots of interrupts.

Thanks for taking the time to write a detailed response.  I asked because I got GIC version of the UG1209 demo application working fine, but it seems like the AXI Interrupt Controller version doesn't run the interrupt handler -- all of the initializations are successful but no interrupt is fired.  So more work to be done there, but at least I have a better understanding of why the part may be chosen for use in a design.

If it initialized successfully, you might be closer than you think.  Looking at the UG1209 demo, it appears to be a Linux project, so I would recommend double checking dmesg to ensure that you aren't getting any error messages from a function call to xilinx_intc_of_init().  Assuming initialization was successful, I would move on and check the registers of the AXI Interrupt Controller.  Probably the easiest way to do this is by using the devmem command line utility.  To use devmem, you will need to know the base address of the AXI Interrupt Controller.  One way to find this out is by checking the devicetree in petalinux.  For example, the address of the AXI Interrupt Controller in this devicetree is 0x41200000.  Yours will probably be different though.  You can also get this information in Vivado's register space tab or potentially in /sys/bus/platform/devices after booting the Ultra96V2.  Once you have the base address, start checking each register in the AXI Interrupt Controller's register space.  The first one I would check is the Interrupt Enable Register (IER) at address offset 0x14.  You can do this by combining the base address with the offset address (0x41200000 + 0x14 = 0x41200014), and then calling "devmem 0x41200014".  If this command returns all zeros, it means that all the interrupts are disabled.  To enable your first interrupt, call something like "devmem 0x41200014 8 0x01".  The "8" means you are only writing to the first eight bits of the register, and "0x01" is the value of these eight bits which should enable the first interrupt for you.  At this point, assuming your timer is initialized properly and assuming it is the first interrupt on the controller, I would suspect that your interrupt handler should be working.  A great way to check this is by calling "cat /proc/interrupts", and checking if the timer interrupt is incrementing at 1Hz in one of the CPU[0-3] columns.  Feel free to try this, and if it doesn't work, I might have some other ideas, but good luck with everything!

I'm running this standalone, on the R5.  I've gone through the example in the 1209 document, and the GIC version of it worked right away.  Building a hardware platform with the AXI Intc in it, the conditional compilation macros in the 1209 example switch over to the Intc specific code.  There it runs through the Initialization, SelfTest, Connect and Start functions returning XST_SUCCESS for each one.  So far so good it would seem.  But, the handler isn't being called.  I should note that rather than GPIO, I modified the example to have an AXI Timer trigger an interrupt at 1 Hz.  I was reading the pg099 document you referenced above, and saw the IER flag.  I would've thought that Initialize would take care of setting it appropriately, but that may not be a correct assumption.

As a reference, attached is the block diagram.  This is the same setup as when I had the interrupt pin of the timer go straight into the Zynq block int pin.  The concat block in this case is superfluous.

My apologies, I skimmed over the introduction for the PG1209 demo, saw the Linux section, but overlooked the R5 standalone section.  Looking at your block diagram, everything looks fine to me.  Looking at the code in timer_psled_r5.c, I have a better sense of what you are describing now.  It sounds like your project is detecting "#ifdef XPAR_INTC_0_DEVICE_ID" which is a good sign on ln433.  I also think you're correct that the IER is getting set properly.  I think this is done with the following line of code:  "XIntc_Enable(IntcInstancePtr, IntrID)" on ln470.

Just before this line, there is a call to "Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE)" on ln462.  I wasn't exactly sure what XIN_REAL_MODE does, so I looked that up.  Apparently the macros XIN_REAL_MODE and XIN_SIMULATION_MODE toggles simulation mode and hardware mode according to xint.c.  In the process of looking this up, I stumbled across answer record 25081 which seems to suggest that these macros got flipped.  Would you mind trying the change described in this answer record?  It might not be the issue, but I think it is worth trying before digging deeper.

My apologies, I skimmed over the introduction for the PG1209 demo, saw the Linux section, but overlooked the R5 standalone section.  Looking at your block diagram, everything looks fine to me.  Looking at the code in timer_psled_r5.c, I have a better sense of what you are describing now.  It sounds like your project is detecting "#ifdef XPAR_INTC_0_DEVICE_ID" which is a good sign on ln433.  I also think you're correct that the IER is getting set properly.  I think this is done with the following line of code:  "XIntc_Enable(IntcInstancePtr, IntrID)" on ln470.

Just before this line, there is a call to "Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE)" on ln462.  I wasn't exactly sure what XIN_REAL_MODE does, so I looked that up.  Apparently the macros XIN_REAL_MODE and XIN_SIMULATION_MODE toggles simulation mode and hardware mode according to xint.c.  In the process of looking this up, I stumbled across answer record 25081 which seems to suggest that these macros got flipped.  Would you mind trying the change described in this answer record?  It might not be the issue, but I think it is worth trying before digging deeper.

I gave that a try, and it didn't work.  Interestingly, I came across this question in the support forums where the poster had a similar issue with the AXI Intc, in his/her case trying to tie it to a DMA controller.  The poster observed that the GIC method worked, but not the INTC method.

I sprinkled some print's in the conditionals where it checks for XST_FAILURE just to verify all of the functions are returning success, which the appear to be. My first concern was that the BD was somehow in error, but it doesn't appear to be.  So that leaves the code.  Perhaps the next thing to do is to read the value of the registers in the INTC, as you suggested above, just to verify that things are indeed being set as intended.

Called Xil_In32(0x80000008) (AXI Interrupt Controller starts at 0x8000_0000, if I'm reading the Address Editor in Vivado correctly), and per pg099, 0x8 is the offset to the IER.  The Xil_In32() returns 0x1, which would indicate that the interrupt is active, so now I'm thinking it has to be in code somewhere.  The program is a lightly modified version of timer_psled_r5.c (basically removing the UART stuff).  Perhaps I stepped on something important compared to the original.

The address of the AXI Intc:

Good catch, I had the wrong offset for the IER.  Everything you just showed looks correct.  Reading 0x80000008 and getting 0x1 is a really good sign,  seems to confirm that the timer interrupt is enabled.

I've been reading the register descriptions a little more closely, and either I am misinterpreting some of them, or there are some inconsistencies in the documentation.  I'll do my best to describe what I think is happening, but without testing, I could be wrong.  Originally, I thought the IER enabled the IRQ at the output of the AXI Interrupt Controller IP because page 18 of PG099 says "Disabling an active interrupt prevents that interrupt from affecting the irq output, but as soon as it is re-enabled the interrupt immediately sets the irq output."  I think that statement is misguided.  If you look at Figure 1-1, there are three main stages for all interrupts (ie not AXI-lite):  (1) Interrupt Detection, (2) Register Blocks, (3) Interrupt Generation.  From my understanding, interrupts will always be detected, but the IER register block will determine whether or not the IRQ reaches the interrupt generator stage.  In conjunction with the IER, I think you also need to configure the master enable register (MER) to get the correct output.  In my opinion, this was a bit of an omission from the documentation in regards to the behavior of the IER.  All that to say, I think you should check the MER register in similar manner.  Specifically, I believe that MER[1:0] needs to equal 2'b11.  These two bits are also called hardware interrupt enable (HIE) and master irq enable (ME).  Optionally, you can try setting HIE=0 (ie MER[1:0]=2'b01) so that you can test the interrupt with software before involving hardware.  If you do so, just keep in mind that you might have to reset the core.

Basically, try running through this programming sequence.  Here is an example:

1. Configure IER[0] = 1'b1.  You have already done this by checking that the 0x80000008 register returns 0x1.
2. Configure MER[1:0] = 2'b01.  This should be the 0x8000001C register.  Warning:  if MER[1] already equaled 1'b1 before this operation, then you will have to reset the IP first.  This is because the MER[1] bit cannot be written to again once it is set.
3. Configure ISR[0] = 1'b1.  This should be the 0x80000000 register.  Doesn't matter which bit you write to, just force any bit in this register to equal 1.  This should trigger your interrupt handler (Note: this is "software" driven because it is triggered by axi-lite).
4. Configure MER[1:0] = 2'b11.  This should be the 0x8000001C register.  This should trigger your interrupt handler (Note: this is "hardware" driven because it is trigger by the net connecting the AXI Timer and the AXI Interrupt Controller).

This should almost certainly work if a handler is setup correctly, but if you want to stick with more general API, then I would look at the code you changed more carefully.  I suspect that you might have deleted the GIC's initialization code in the SetupInterruptSystem function when removing the UART code.  To be fair, Xilinx's variable names did not help at all.  For example, "INTC *UartIntcInstancePtr" may look like a uart instance but it is actually an AXI Interrupt Controller instance.

I notice too that the example code from Xilinx references XPAR_FABRIC_AXI_TIMER_0_INTERRUPT_INTR.  I don't have that in my xparameters.h.  The closet thing I have is a XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR which is #define'd as 0U.

My interrupt settings in the Zynq US+ Processing System is:

Other than that, the settings for the other IP's, notable AXI Interrupt Controller, are default.  I recreated the BD from scratch:

I ran through the procedure you outlined above -- all the registers were configured as you would expect for the handler to be called.  In the software, the timer instance is connected to the interrupt controller instance, and the timer handler is connected to the timer instance, so things should, as you point out work.  The Uart* functions I removed don't impact the code, as there is an interrupt setup routine for the timer counter.  I have seen slight variations with this program from Xilinx, but they all follow the same API calls.  Not sure what else to do.  The missing XPAR_FABRIC_AXI_TIMER_0_INTERRUPT_INTR bothers me, but maybe that symbol is relevant to the Zynq-7000 and not US+?  To reiterate, the GIC version of the code works.  If you're interested, I've attached the source code and the xparameters.h file for reference.

Thanks again for taking the time to look through this with me.  I have working solution with the GIC method, but (a) this should work and (b) I may need to use this method one day.

#include "xparameters.h"
#include "xtmrctr.h"
#include "xil_exception.h"
#include <stdio.h>
#include "math.h"
#include "xplatform_info.h"
#include "xuartps.h"
#include "xil_printf.h"
#include "xgpiops.h"
#include "xil_io.h"
#ifdef XPAR_INTC_0_DEVICE_ID
#include "xintc.h"
#include <stdio.h>
#else
#include "xscugic.h"
#endif
#include "xtime_l.h"

/************************** Constant Definitions *****************************/
/*
 * The following constants map to the XPAR parameters created in the
 * xparameters.h file. They are only defined here such that a user can easily
 * change all the needed parameters in one place.
 */
#define TMRCTR_DEVICE_ID	XPAR_TMRCTR_0_DEVICE_ID
//#define TMRCTR_INTERRUPT_ID	XPAR_FABRIC_AXI_TIMER_0_INTERRUPT_INTR
#define TMRCTR_INTERRUPT_ID		XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR
#ifdef XPAR_INTC_0_DEVICE_ID
#define INTC_DEVICE_ID		XPAR_INTC_0_DEVICE_ID
#else
#define INTC_DEVICE_ID		XPAR_SCUGIC_SINGLE_DEVICE_ID
#endif /* XPAR_INTC_0_DEVICE_ID */

/*
 * The following constant determines which timer counter of the device that is
 * used for this example, there are currently 2 timer counters in a device
 * and this example uses the first one, 0, the timer numbers are 0 based
 */
#define TIMER_CNTR_0	 0

#ifdef XPAR_INTC_0_DEVICE_ID
#define INTC		XIntc
#define INTC_HANDLER	XIntc_InterruptHandler
#else
#define INTC		XScuGic
#define INTC_HANDLER	XScuGic_InterruptHandler
#endif /* XPAR_INTC_0_DEVICE_ID */

/*
 * The following constant is used to set the reset value of the timer counter,
 * making this number larger reduces the because it is the value the timer counter is loaded with when it is started
 */
//#define RESET_VALUE		0xF4143E01			//Time interval of 2 secs
#define RESET_VALUE		0xFA0A1F01			//Time Interval of 1 sec

/*
 * The following constants map to the XPAR parameters created in the
 * xparameters.h file. They are defined here such that a user can easily
 * change all the needed parameters in one place.
 */
#ifdef XPAR_INTC_0_DEVICE_ID
#define INTC		XIntc
#define UART_DEVICE_ID		XPAR_XUARTPS_1_DEVICE_ID
#define INTC_DEVICE_ID		XPAR_INTC_0_DEVICE_ID
#define UART_INT_IRQ_ID		XPAR_INTC_0_UARTPS_1_VEC_ID
#else
//#define INTC		XScuGic
//#define UART_DEVICE_ID		XPAR_XUARTPS_1_DEVICE_ID
#define INTC_DEVICE_ID		XPAR_SCUGIC_SINGLE_DEVICE_ID
//#define UART_INT_IRQ_ID		XPAR_XUARTPS_1_INTR
#endif

/************************** Function Prototypes ******************************/

int TmrControllerSetup(INTC* IntcInstancePtr,
			XTmrCtr* InstancePtr,
			u16 DeviceId,
			u16 IntrId,
			u8 TmrCtrNumber);

static int TmrCtrSetupIntrSystem(INTC* IntcInstancePtr,
				XTmrCtr* InstancePtr,
				u16 DeviceId,
				u16 IntrId,
				u8 TmrCtrNumber);

void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber);

void TmrCtrDisableIntr(INTC* IntcInstancePtr, u16 IntrId);



/************************** Variable Definitions *****************************/

//static int TimerExpired;

INTC InterruptController;  /* The instance of the Interrupt Controller */

XTmrCtr TimerCounterInst;   /* The instance of the Timer Counter */

XTime tStart, tEnd;

int main(void)
{
	int Status;

	print("*** Application Start ***\n\r");

	Status = TmrControllerSetup(&InterruptController,
					  &TimerCounterInst,
					  TMRCTR_DEVICE_ID,
					  TMRCTR_INTERRUPT_ID,
					  TIMER_CNTR_0);

	if (Status != XST_SUCCESS)
	{       print("TmrControllerSetup failed\n\r");
			return XST_FAILURE;
	}

	XTmrCtr_Start(&TimerCounterInst, TIMER_CNTR_0);

	while (1)
	{
		//print(".\r\n");
	}
	return 0;
}


int TmrControllerSetup(INTC* IntcInstancePtr,
			XTmrCtr* TmrCtrInstancePtr,
			u16 DeviceId,
			u16 IntrId,
			u8 TmrCtrNumber)
{
	int Status;
	print("TmrControllerSetup\r\n");
	/*
	 * Initialize the timer counter so that it's ready to use,
	 * specify the device ID that is generated in xparameters.h
	 */
	Status = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId);
	if (Status != XST_SUCCESS)
	{
		print("XTmrCtr_Initialize failed\n\r");
		return XST_FAILURE;
	}

	/*
	 * Perform a self-test to ensure that the hardware was built
	 * correctly, use the 1st timer in the device (0)
	 */
	Status = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber);
	if (Status != XST_SUCCESS)
	{
		print("XTmrCtr_SelfTest failed\n\r");
		return XST_FAILURE;
	}

	/*
	 * Connect the timer counter to the interrupt subsystem such that
	 * interrupts can occur.  This function is application specific.
	 */
	Status = TmrCtrSetupIntrSystem(IntcInstancePtr,
					TmrCtrInstancePtr,
					DeviceId,
					IntrId,
					TmrCtrNumber);
	if (Status != XST_SUCCESS)
	{
		print("Unable to connect timer to interrupt subsystem\n\r");
		return XST_FAILURE;
	}

	/*
	 * Setup the handler for the timer counter that will be called from the
	 * interrupt context when the timer expires, specify a pointer to the
	 * timer counter driver instance as the callback reference so the handler
	 * is able to access the instance data
	 */
	XTmrCtr_SetHandler(TmrCtrInstancePtr, TimerCounterHandler,
					   TmrCtrInstancePtr);
	/*
	 * Enable the interrupt of the timer counter so interrupts will occur
	 * and use auto reload mode such that the timer counter will reload
	 * itself automatically and continue repeatedly, without this option
	 * it would expire once only
	 */
	XTmrCtr_SetOptions(TmrCtrInstancePtr,TmrCtrNumber,
	(XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION | XTC_CSR_INT_OCCURED_MASK ));

	/*
	 * Set a reset value for the timer counter such that it will expire
	 * eariler than letting it roll over from 0, the reset value is loaded
	 * into the timer counter when it is started
	 */
	XTmrCtr_SetResetValue(TmrCtrInstancePtr, TmrCtrNumber, RESET_VALUE);

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
* This function is the handler which performs processing for the timer counter.
* It is called from an interrupt context such that the amount of processing
* performed should be minimized.  It is called when the timer counter expires
* if interrupts are enabled.
*
* This handler is application specific to handle timer counter interrupts.
* In this case the handler stops the timer and indicates the timer counter
* state to the application by setting the TimerExpired flag to high.
*
* @param	CallBackRef is a pointer to the callback function
* @param	TmrCtrNumber is the number of the timer to which this
*		handler is associated with.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
void TimerCounterHandler(void *CallBackRef, u8 TmrCtrNumber)
{
	XTmrCtr *InstancePtr = (XTmrCtr *)CallBackRef;
	if (NULL == InstancePtr) {
		print("InstancePTR is NULL \n \r ");
			return;
		}
	//XTmrCtr_Stop(InstancePtr,TmrCtrNumber);
	//TimerExpired = 1;
	XTime_GetTime(&tStart);
	printf("Interrupt triggered: %lu\n", tStart);
}

/*****************************************************************************/
/**
* This function setups the interrupt system such that interrupts can occur
* for the timer counter. This function is application specific since the actual
* system may or may not have an interrupt controller.  The timer counter could
* be directly connected to a processor without an interrupt controller.  The
* user should modify this function to fit the application.
*
* @param	IntcInstancePtr is a pointer to the Interrupt Controller
*		driver Instance.
* @param	TmrCtrInstancePtr is a pointer to the XTmrCtr driver Instance.
* @param	DeviceId is the XPAR_<TmrCtr_instance>_DEVICE_ID value from
*		xparameters.h.
* @param	IntrId is XPAR_<INTC_instance>_<TmrCtr_instance>_VEC_ID
*		value from xparameters.h.
* @param	TmrCtrNumber is the number of the timer to which this
*		handler is associated with.
*
* @return	XST_SUCCESS if the Test is successful, otherwise XST_FAILURE.
*
* @note		This function contains an infinite loop such that if interrupts
*		are not working it may never return.
*
******************************************************************************/
static int TmrCtrSetupIntrSystem(INTC* IntcInstancePtr,
				 XTmrCtr* TmrCtrInstancePtr,
				 u16 DeviceId,
				 u16 IntrId,
				 u8 TmrCtrNumber)
{
	 int Status;

#ifdef XPAR_INTC_0_DEVICE_ID

	/*
	 * Initialize the interrupt controller driver so that
	 * it's ready to use, specify the device ID that is generated in
	 * xparameters.h
	 */
	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Connect a device driver handler that will be called when an interrupt
	 * for the device occurs, the device driver handler performs the specific
	 * interrupt processing for the device
	 */
	Status = XIntc_Connect(IntcInstancePtr, IntrId,
				(XInterruptHandler)XTmrCtr_InterruptHandler,
				(void *)TmrCtrInstancePtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Start the interrupt controller such that interrupts are enabled for
	 * all devices that cause interrupts, specific real mode so that
	 * the timer counter can cause interrupts thru the interrupt controller.
	 */
	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Enable the interrupt for the timer counter
	 */
	XIntc_Enable(IntcInstancePtr, IntrId);

#else

	XScuGic_Config *IntcConfig;

	/*
	 * Initialize the interrupt controller driver so that it is ready to
	 * use.
	 */
	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
	if (NULL == IntcConfig) {
		return XST_FAILURE;
	}

	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
					IntcConfig->CpuBaseAddress);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	XScuGic_SetPriorityTriggerType(IntcInstancePtr, IntrId,
					0xA0, 0x3);

	/*
	 * Connect the interrupt handler that will be called when an
	 * interrupt occurs for the device.
	 */
	Status = XScuGic_Connect(IntcInstancePtr, IntrId,
				 (Xil_ExceptionHandler)XTmrCtr_InterruptHandler,
				 TmrCtrInstancePtr);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	/*
	 * Enable the interrupt for the Timer device.
	 */
	XScuGic_Enable(IntcInstancePtr, IntrId);
#endif /* XPAR_INTC_0_DEVICE_ID */


	/*
	 * Initialize the exception table.
	 */
	Xil_ExceptionInit();

	/*
	 * Register the interrupt controller handler with the exception table.
	 */
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
					(Xil_ExceptionHandler)
					INTC_HANDLER,
					IntcInstancePtr);

	/*
	 * Enable non-critical exceptions.
	 */
	Xil_ExceptionEnable();

	return XST_SUCCESS;
}

/******************************************************************************/
/**
*
* This function disables the interrupts for the Timer.
*
* @param	IntcInstancePtr is a reference to the Interrupt Controller
*		driver Instance.
* @param	IntrId is XPAR_<INTC_instance>_<Timer_instance>_VEC_ID
*		value from xparameters.h.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
void TmrCtrDisableIntr(INTC* IntcInstancePtr, u16 IntrId)
{
	/*
	 * Disable the interrupt for the timer counter
	 */
#ifdef XPAR_INTC_0_DEVICE_ID
	XIntc_Disable(IntcInstancePtr, IntrId);
#else
	/* Disconnect the interrupt */
	XScuGic_Disable(IntcInstancePtr, IntrId);
	XScuGic_Disconnect(IntcInstancePtr, IntrId);
#endif

	return;
}

#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

/* Definition for CPU ID */
#define XPAR_CPU_ID 0U

/* Definitions for peripheral PSU_CORTEXR5_0 */
#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 500000000


/******************************************************************/

/* Canonical definitions for peripheral PSU_CORTEXR5_0 */
#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 500000000


/******************************************************************/

 /* Definition for PSS REF CLK FREQUENCY */
#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333333U

#include "xparameters_ps.h"

#define XPS_BOARD_ULTRA96V2


/* Number of Fabric Resets */
#define XPAR_NUM_FABRIC_RESETS 1

#define STDIN_BASEADDRESS 0xFF010000
#define STDOUT_BASEADDRESS 0xFF010000

/******************************************************************/

/* Platform specific definitions */
#define PLATFORM_ZYNQMP
 
/* Definitions for debug logic configuration in lockstep mode */
#define LOCKSTEP_MODE_DEBUG 0U
 
/* Definitions for sleep timer configuration */
#define SLEEP_TIMER_BASEADDR XPAR_PSU_TTC_9_BASEADDR
#define SLEEP_TIMER_FREQUENCY XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ
#define XSLEEP_TTC_INSTANCE 3
#define XSLEEP_TIMER_IS_DEFAULT_TIMER
 
/* Definitions for processor access to RPU/IOU slcr address space*/
#define PROCESSOR_ACCESS_VALUE 255
 
/******************************************************************/
/* Definitions for driver AVBUF */
#define XPAR_XAVBUF_NUM_INSTANCES 1

/* Definitions for peripheral PSU_DP */
#define XPAR_PSU_DP_DEVICE_ID 0
#define XPAR_PSU_DP_BASEADDR 0xFD4A0000
#define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF


/******************************************************************/

/* Canonical definitions for peripheral PSU_DP */
#define XPAR_XAVBUF_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID
#define XPAR_XAVBUF_0_BASEADDR 0xFD4A0000
#define XPAR_XAVBUF_0_HIGHADDR 0xFD4AFFFF


/******************************************************************/

/* Definitions for driver AXIPMON */
#define XPAR_XAXIPMON_NUM_INSTANCES 4U

/* Definitions for peripheral PSU_APM_0 */
#define XPAR_PSU_APM_0_DEVICE_ID 0U
#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000U
#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFFU
#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32U
#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32U
#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1U
#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6U
#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10U
#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1U
#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0U
#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32U
#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56U
#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1U
#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1U
#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1U
#define XPAR_PSU_APM_0_ENABLE_PROFILE 0U
#define XPAR_PSU_APM_0_ENABLE_TRACE 0U
#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000U
#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000U
#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1U


/* Definitions for peripheral PSU_APM_1 */
#define XPAR_PSU_APM_1_DEVICE_ID 1U
#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000U
#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFFU
#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32U
#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32U
#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1U
#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1U
#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3U
#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1U
#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0U
#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32U
#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56U
#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1U
#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1U
#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1U
#define XPAR_PSU_APM_1_ENABLE_PROFILE 0U
#define XPAR_PSU_APM_1_ENABLE_TRACE 0U
#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000U
#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000U
#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1U


/* Definitions for peripheral PSU_APM_2 */
#define XPAR_PSU_APM_2_DEVICE_ID 2U
#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000U
#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFFU
#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32U
#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32U
#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1U
#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1U
#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3U
#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1U
#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0U
#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32U
#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56U
#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1U
#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1U
#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1U
#define XPAR_PSU_APM_2_ENABLE_PROFILE 0U
#define XPAR_PSU_APM_2_ENABLE_TRACE 0U
#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000U
#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000U
#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1U


/* Definitions for peripheral PSU_APM_5 */
#define XPAR_PSU_APM_5_DEVICE_ID 3U
#define XPAR_PSU_APM_5_BASEADDR 0xFD490000U
#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFFU
#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32U
#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32U
#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1U
#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1U
#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3U
#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1U
#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0U
#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32U
#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56U
#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1U
#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1U
#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1U
#define XPAR_PSU_APM_5_ENABLE_PROFILE 0U
#define XPAR_PSU_APM_5_ENABLE_TRACE 0U
#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000U
#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000U
#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1U


/******************************************************************/

/* Canonical definitions for peripheral PSU_APM_0 */
#define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID
#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000U
#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFFU
#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32U
#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32U
#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1U
#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6U
#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10U
#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1U
#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0U
#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32U
#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56U
#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1U
#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1U
#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1U
#define XPAR_AXIPMON_0_ENABLE_PROFILE 0U
#define XPAR_AXIPMON_0_ENABLE_TRACE 0U
#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000U
#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000U
#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1U

/* Canonical definitions for peripheral PSU_APM_1 */
#define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID
#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000U
#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFFU
#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32U
#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32U
#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1U
#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1U
#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3U
#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1U
#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0U
#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32U
#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56U
#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1U
#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1U
#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1U
#define XPAR_AXIPMON_1_ENABLE_PROFILE 0U
#define XPAR_AXIPMON_1_ENABLE_TRACE 0U
#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000U
#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000U
#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1U

/* Canonical definitions for peripheral PSU_APM_2 */
#define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID
#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000U
#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFFU
#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32U
#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32U
#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1U
#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1U
#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3U
#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1U
#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0U
#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32U
#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56U
#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1U
#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1U
#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1U
#define XPAR_AXIPMON_2_ENABLE_PROFILE 0U
#define XPAR_AXIPMON_2_ENABLE_TRACE 0U
#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000U
#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000U
#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1U

/* Canonical definitions for peripheral PSU_APM_5 */
#define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID
#define XPAR_AXIPMON_3_BASEADDR 0xFD490000U
#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFFU
#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32U
#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32U
#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1U
#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1U
#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3U
#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1U
#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0U
#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32U
#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56U
#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1U
#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1U
#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1U
#define XPAR_AXIPMON_3_ENABLE_PROFILE 0U
#define XPAR_AXIPMON_3_ENABLE_TRACE 0U
#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000U
#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000U
#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1U


/******************************************************************/

/* Definitions for driver CSUDMA */
#define XPAR_XCSUDMA_NUM_INSTANCES 1

/* Definitions for peripheral PSU_CSUDMA */
#define XPAR_PSU_CSUDMA_DEVICE_ID 0
#define XPAR_PSU_CSUDMA_BASEADDR 0xFFC80000
#define XPAR_PSU_CSUDMA_HIGHADDR 0xFFC9FFFF
#define XPAR_PSU_CSUDMA_CSUDMA_CLK_FREQ_HZ 0


/******************************************************************/

#define XPAR_PSU_CSUDMA_DMATYPE 0
/* Canonical definitions for peripheral PSU_CSUDMA */
#define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSU_CSUDMA_DEVICE_ID
#define XPAR_XCSUDMA_0_BASEADDR 0xFFC80000
#define XPAR_XCSUDMA_0_HIGHADDR 0xFFC9FFFF
#define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0


/******************************************************************/

/* Definitions for driver DDRCPSU */
#define XPAR_XDDRCPSU_NUM_INSTANCES 1

/* Definitions for peripheral PSU_DDRC_0 */
#define XPAR_PSU_DDRC_0_DEVICE_ID 0
#define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000
#define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF
#define XPAR_PSU_DDRC_0_HAS_ECC 0
#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 266666656


/******************************************************************/

#define XPAR_PSU_DDRC_0_DDR4_ADDR_MAPPING 0
#define XPAR_PSU_DDRC_0_DDR_FREQ_MHZ 533.333313
#define XPAR_PSU_DDRC_0_VIDEO_BUFFER_SIZE 0
#define XPAR_PSU_DDRC_0_BRC_MAPPING 0
#define XPAR_PSU_DDRC_0_DDR_MEMORY_TYPE 5
#define XPAR_PSU_DDRC_0_DDR_MEMORY_ADDRESS_MAP 0
#define XPAR_PSU_DDRC_0_DDR_DATA_MASK_AND_DBI 7
#define XPAR_PSU_DDRC_0_DDR_ADDRESS_MIRRORING 0
#define XPAR_PSU_DDRC_0_DDR_2ND_CLOCK 0
#define XPAR_PSU_DDRC_0_DDR_PARITY 0
#define XPAR_PSU_DDRC_0_DDR_POWER_DOWN_ENABLE 0
#define XPAR_PSU_DDRC_0_CLOCK_STOP 0
#define XPAR_PSU_DDRC_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0
#define XPAR_PSU_DDRC_0_DDR_TEMP_CONTROLLED_REFRESH 0
#define XPAR_PSU_DDRC_0_DDR_MAX_OPERATING_TEMPARATURE 1
#define XPAR_PSU_DDRC_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0
#define XPAR_PSU_DDRC_0_DDR_SELF_REFRESH_ABORT 0
/* Canonical definitions for peripheral PSU_DDRC_0 */
#define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID
#define XPAR_DDRCPSU_0_BASEADDR 0xFD070000
#define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF
#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 266666656


/******************************************************************/

#define XPAR_DDRCPSU_0_DDR4_ADDR_MAPPING 0
#define XPAR_DDRCPSU_0_DDR_FREQ_MHZ 533.333313
#define XPAR_DDRCPSU_0_VIDEO_BUFFER_SIZE 0
#define XPAR_DDRCPSU_0_BRC_MAPPING 0
#define XPAR_DDRCPSU_0_DDR_MEMORY_TYPE 5
#define XPAR_DDRCPSU_0_DDR_MEMORY_ADDRESS_MAP 0
#define XPAR_DDRCPSU_0_DDR_DATA_MASK_AND_DBI 7
#define XPAR_DDRCPSU_0_DDR_ADDRESS_MIRRORING 0
#define XPAR_DDRCPSU_0_DDR_2ND_CLOCK 0
#define XPAR_DDRCPSU_0_DDR_PARITY 0
#define XPAR_DDRCPSU_0_DDR_POWER_DOWN_ENABLE 0
#define XPAR_DDRCPSU_0_CLOCK_STOP 0
#define XPAR_DDRCPSU_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0
#define XPAR_DDRCPSU_0_DDR_TEMP_CONTROLLED_REFRESH 0
#define XPAR_DDRCPSU_0_DDR_MAX_OPERATING_TEMPARATURE 1
#define XPAR_DDRCPSU_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0
#define XPAR_DDRCPSU_0_DDR_SELF_REFRESH_ABORT 0
/* Definitions for driver DPDMA */
#define XPAR_XDPDMA_NUM_INSTANCES 1

/* Definitions for peripheral PSU_DPDMA */
#define XPAR_PSU_DPDMA_DEVICE_ID 0
#define XPAR_PSU_DPDMA_BASEADDR 0xFD4C0000
#define XPAR_PSU_DPDMA_HIGHADDR 0xFD4CFFFF


/******************************************************************/

/* Canonical definitions for peripheral PSU_DPDMA */
#define XPAR_XDPDMA_0_DEVICE_ID XPAR_PSU_DPDMA_DEVICE_ID
#define XPAR_XDPDMA_0_BASEADDR 0xFD4C0000
#define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF


/******************************************************************/


/* Definitions for peripheral PSU_AFI_0 */
#define XPAR_PSU_AFI_0_S_AXI_BASEADDR 0xFD360000
#define XPAR_PSU_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF


/* Definitions for peripheral PSU_AFI_1 */
#define XPAR_PSU_AFI_1_S_AXI_BASEADDR 0xFD370000
#define XPAR_PSU_AFI_1_S_AXI_HIGHADDR 0xFD37FFFF


/* Definitions for peripheral PSU_AFI_2 */
#define XPAR_PSU_AFI_2_S_AXI_BASEADDR 0xFD380000
#define XPAR_PSU_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF


/* Definitions for peripheral PSU_AFI_3 */
#define XPAR_PSU_AFI_3_S_AXI_BASEADDR 0xFD390000
#define XPAR_PSU_AFI_3_S_AXI_HIGHADDR 0xFD39FFFF


/* Definitions for peripheral PSU_AFI_4 */
#define XPAR_PSU_AFI_4_S_AXI_BASEADDR 0xFD3A0000
#define XPAR_PSU_AFI_4_S_AXI_HIGHADDR 0xFD3AFFFF


/* Definitions for peripheral PSU_AFI_5 */
#define XPAR_PSU_AFI_5_S_AXI_BASEADDR 0xFD3B0000
#define XPAR_PSU_AFI_5_S_AXI_HIGHADDR 0xFD3BFFFF


/* Definitions for peripheral PSU_AFI_6 */
#define XPAR_PSU_AFI_6_S_AXI_BASEADDR 0xFF9B0000
#define XPAR_PSU_AFI_6_S_AXI_HIGHADDR 0xFF9BFFFF


/* Definitions for peripheral PSU_APU */
#define XPAR_PSU_APU_S_AXI_BASEADDR 0xFD5C0000
#define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF


/* Definitions for peripheral PSU_CCI_GPV */
#define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000
#define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF


/* Definitions for peripheral PSU_CCI_REG */
#define XPAR_PSU_CCI_REG_S_AXI_BASEADDR 0xFD5E0000
#define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF


/* Definitions for peripheral PSU_CRL_APB */
#define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000
#define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF


/* Definitions for peripheral PSU_CSU_0 */
#define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000
#define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF


/* Definitions for peripheral PSU_CTRL_IPI */
#define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000
#define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF


/* Definitions for peripheral PSU_DDR_PHY */
#define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000
#define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF


/* Definitions for peripheral PSU_DDR_QOS_CTRL */
#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_BASEADDR 0xFD090000
#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_HIGHADDR 0xFD09FFFF


/* Definitions for peripheral PSU_DDR_XMPU0_CFG */
#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_BASEADDR 0xFD000000
#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_HIGHADDR 0xFD00FFFF


/* Definitions for peripheral PSU_DDR_XMPU1_CFG */
#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_BASEADDR 0xFD010000
#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_HIGHADDR 0xFD01FFFF


/* Definitions for peripheral PSU_DDR_XMPU2_CFG */
#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_BASEADDR 0xFD020000
#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_HIGHADDR 0xFD02FFFF


/* Definitions for peripheral PSU_DDR_XMPU3_CFG */
#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_BASEADDR 0xFD030000
#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_HIGHADDR 0xFD03FFFF


/* Definitions for peripheral PSU_DDR_XMPU4_CFG */
#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_BASEADDR 0xFD040000
#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_HIGHADDR 0xFD04FFFF


/* Definitions for peripheral PSU_DDR_XMPU5_CFG */
#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_BASEADDR 0xFD050000
#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF


/* Definitions for peripheral PSU_EFUSE */
#define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000
#define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF


/* Definitions for peripheral PSU_FPD_GPV */
#define XPAR_PSU_FPD_GPV_S_AXI_BASEADDR 0xFD700000
#define XPAR_PSU_FPD_GPV_S_AXI_HIGHADDR 0xFD7FFFFF


/* Definitions for peripheral PSU_FPD_SLCR */
#define XPAR_PSU_FPD_SLCR_S_AXI_BASEADDR 0xFD610000
#define XPAR_PSU_FPD_SLCR_S_AXI_HIGHADDR 0xFD68FFFF


/* Definitions for peripheral PSU_FPD_SLCR_SECURE */
#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_BASEADDR 0xFD690000
#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFD6CFFFF


/* Definitions for peripheral PSU_FPD_XMPU_CFG */
#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_BASEADDR 0xFD5D0000
#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_HIGHADDR 0xFD5DFFFF


/* Definitions for peripheral PSU_FPD_XMPU_SINK */
#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_BASEADDR 0xFD4F0000
#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_HIGHADDR 0xFD4FFFFF


/* Definitions for peripheral PSU_GPU */
#define XPAR_PSU_GPU_S_AXI_BASEADDR 0xFD4B0000
#define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF


/* Definitions for peripheral PSU_IOU_SCNTR */
#define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000
#define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF


/* Definitions for peripheral PSU_IOU_SCNTRS */
#define XPAR_PSU_IOU_SCNTRS_S_AXI_BASEADDR 0xFF260000
#define XPAR_PSU_IOU_SCNTRS_S_AXI_HIGHADDR 0xFF26FFFF


/* Definitions for peripheral PSU_IOUSECURE_SLCR */
#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_BASEADDR 0xFF240000
#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_HIGHADDR 0xFF24FFFF


/* Definitions for peripheral PSU_IOUSLCR_0 */
#define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000
#define XPAR_PSU_IOUSLCR_0_S_AXI_HIGHADDR 0xFF23FFFF


/* Definitions for peripheral PSU_LPD_SLCR */
#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000
#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF


/* Definitions for peripheral PSU_LPD_SLCR_SECURE */
#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_BASEADDR 0xFF4B0000
#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFF4DFFFF


/* Definitions for peripheral PSU_LPD_XPPU */
#define XPAR_PSU_LPD_XPPU_S_AXI_BASEADDR 0xFF980000
#define XPAR_PSU_LPD_XPPU_S_AXI_HIGHADDR 0xFF99FFFF


/* Definitions for peripheral PSU_LPD_XPPU_SINK */
#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_BASEADDR 0xFF9C0000
#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_HIGHADDR 0xFF9CFFFF


/* Definitions for peripheral PSU_MBISTJTAG */
#define XPAR_PSU_MBISTJTAG_S_AXI_BASEADDR 0xFFCF0000
#define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF


/* Definitions for peripheral PSU_MESSAGE_BUFFERS */
#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_BASEADDR 0xFF990000
#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_HIGHADDR 0xFF99FFFF


/* Definitions for peripheral PSU_OCM */
#define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000
#define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF


/* Definitions for peripheral PSU_OCM_RAM_0 */
#define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000
#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFFFFFF


/* Definitions for peripheral PSU_OCM_XMPU_CFG */
#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000
#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF


/* Definitions for peripheral PSU_PMU_GLOBAL_0 */
#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000
#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF


/* Definitions for peripheral PSU_R5_0_ATCM */
#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0x00000000
#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0x0000FFFF


/* Definitions for peripheral PSU_R5_0_BTCM */
#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0x00020000
#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0x0002FFFF


/* Definitions for peripheral PSU_R5_DDR_0 */
#define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF


/* Definitions for peripheral PSU_R5_TCM_RAM_0 */
#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x0003FFFF


/* Definitions for peripheral PSU_RPU */
#define XPAR_PSU_RPU_S_AXI_BASEADDR 0xFF9A0000
#define XPAR_PSU_RPU_S_AXI_HIGHADDR 0xFF9AFFFF


/* Definitions for peripheral PSU_RSA */
#define XPAR_PSU_RSA_S_AXI_BASEADDR 0xFFCE0000
#define XPAR_PSU_RSA_S_AXI_HIGHADDR 0xFFCEFFFF


/* Definitions for peripheral PSU_SERDES */
#define XPAR_PSU_SERDES_S_AXI_BASEADDR 0xFD400000
#define XPAR_PSU_SERDES_S_AXI_HIGHADDR 0xFD47FFFF


/* Definitions for peripheral PSU_SIOU */
#define XPAR_PSU_SIOU_S_AXI_BASEADDR 0xFD3D0000
#define XPAR_PSU_SIOU_S_AXI_HIGHADDR 0xFD3DFFFF


/* Definitions for peripheral PSU_SMMU_GPV */
#define XPAR_PSU_SMMU_GPV_S_AXI_BASEADDR 0xFD800000
#define XPAR_PSU_SMMU_GPV_S_AXI_HIGHADDR 0xFDFFFFFF


/* Definitions for peripheral PSU_SMMU_REG */
#define XPAR_PSU_SMMU_REG_S_AXI_BASEADDR 0xFD5F0000
#define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF


/* Definitions for peripheral PSU_USB_0 */
#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFF9D0000
#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFF9DFFFF


/* Definitions for peripheral PSU_USB_1 */
#define XPAR_PSU_USB_1_S_AXI_BASEADDR 0xFF9E0000
#define XPAR_PSU_USB_1_S_AXI_HIGHADDR 0xFF9EFFFF


/******************************************************************/

/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1

/* Definitions for peripheral PSU_GPIO_0 */
#define XPAR_PSU_GPIO_0_DEVICE_ID 0
#define XPAR_PSU_GPIO_0_BASEADDR 0xFF0A0000
#define XPAR_PSU_GPIO_0_HIGHADDR 0xFF0AFFFF


/******************************************************************/

/* Canonical definitions for peripheral PSU_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000
#define XPAR_XGPIOPS_0_HIGHADDR 0xFF0AFFFF


/******************************************************************/

/* Definitions for driver IICPS */
#define XPAR_XIICPS_NUM_INSTANCES 1

/* Definitions for peripheral PSU_I2C_1 */
#define XPAR_PSU_I2C_1_DEVICE_ID 0
#define XPAR_PSU_I2C_1_BASEADDR 0xFF030000
#define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF
#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 100000000


/******************************************************************/

/* Canonical definitions for peripheral PSU_I2C_1 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xFF030000
#define XPAR_XIICPS_0_HIGHADDR 0xFF03FFFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 100000000


/******************************************************************/

/* Definition for input Clock */
#define XPAR_PSU_I2C_1_REF_CLK I2C1_REF
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 1
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_HAS_SIE 1
#define XPAR_XINTC_HAS_CIE 1
#define XPAR_XINTC_HAS_IVR 1
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1

/* Definitions for peripheral AXI_INTC_0 */
#define XPAR_AXI_INTC_0_DEVICE_ID 0
#define XPAR_AXI_INTC_0_BASEADDR 0x80000000
#define XPAR_AXI_INTC_0_HIGHADDR 0x8000FFFF
#define XPAR_AXI_INTC_0_KIND_OF_INTR 0xFFFFFFFE
#define XPAR_AXI_INTC_0_HAS_FAST 0
#define XPAR_AXI_INTC_0_IVAR_RESET_VALUE 0x0000000000000010
#define XPAR_AXI_INTC_0_NUM_INTR_INPUTS 1
#define XPAR_AXI_INTC_0_NUM_SW_INTR 0
#define XPAR_AXI_INTC_0_ADDR_WIDTH 32


/******************************************************************/

#define XPAR_INTC_SINGLE_BASEADDR 0x80000000
#define XPAR_INTC_SINGLE_HIGHADDR 0x8000FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
#define XPAR_AXI_INTC_0_TYPE 0U
#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000001U
#define XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR 0U

/******************************************************************/

/* Canonical definitions for peripheral AXI_INTC_0 */
#define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0x80000000U
#define XPAR_INTC_0_HIGHADDR 0x8000FFFFU
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFFEU
#define XPAR_INTC_0_HAS_FAST 0U
#define XPAR_INTC_0_IVAR_RESET_VALUE 0x0000000000000010U
#define XPAR_INTC_0_NUM_INTR_INPUTS 1U
#define XPAR_INTC_0_NUM_SW_INTR 0U
#define XPAR_INTC_0_ADDR_WIDTH 32U
#define XPAR_INTC_0_INTC_TYPE 0U

#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR

/******************************************************************/

#define  XPAR_XIPIPSU_NUM_INSTANCES  1U

/* Parameter definitions for peripheral psu_ipi_1 */
#define  XPAR_PSU_IPI_1_DEVICE_ID  0U
#define  XPAR_PSU_IPI_1_S_AXI_BASEADDR  0xFF310000U
#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100U
#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0U
#define  XPAR_PSU_IPI_1_INT_ID  65U

/* Canonical definitions for peripheral psu_ipi_1 */
#define  XPAR_XIPIPSU_0_DEVICE_ID	XPAR_PSU_IPI_1_DEVICE_ID
#define  XPAR_XIPIPSU_0_BASE_ADDRESS	XPAR_PSU_IPI_1_S_AXI_BASEADDR
#define  XPAR_XIPIPSU_0_BIT_MASK	XPAR_PSU_IPI_1_BIT_MASK
#define  XPAR_XIPIPSU_0_BUFFER_INDEX	XPAR_PSU_IPI_1_BUFFER_INDEX
#define  XPAR_XIPIPSU_0_INT_ID	XPAR_PSU_IPI_1_INT_ID

#define  XPAR_XIPIPSU_NUM_TARGETS  7U

#define  XPAR_PSU_IPI_0_BIT_MASK  0x00000001U
#define  XPAR_PSU_IPI_0_BUFFER_INDEX  2U
#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100U
#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0U
#define  XPAR_PSU_IPI_2_BIT_MASK  0x00000200U
#define  XPAR_PSU_IPI_2_BUFFER_INDEX  1U
#define  XPAR_PSU_IPI_3_BIT_MASK  0x00010000U
#define  XPAR_PSU_IPI_3_BUFFER_INDEX  7U
#define  XPAR_PSU_IPI_4_BIT_MASK  0x00020000U
#define  XPAR_PSU_IPI_4_BUFFER_INDEX  7U
#define  XPAR_PSU_IPI_5_BIT_MASK  0x00040000U
#define  XPAR_PSU_IPI_5_BUFFER_INDEX  7U
#define  XPAR_PSU_IPI_6_BIT_MASK  0x00080000U
#define  XPAR_PSU_IPI_6_BUFFER_INDEX  7U
/* Target List for referring to processor IPI Targets */

#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0U

#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0U

#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0U

#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0U

#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1U

#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK  XPAR_PSU_IPI_2_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX  2U

#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_3_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  3U
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_4_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  4U
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_5_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  5U
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_6_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  6U

/* Definitions for driver RESETPS and CLOCKPS */
#define XPAR_XCRPSU_NUM_INSTANCES 1U

/* Definitions for peripheral PSU_CR_0 */
#define XPAR_PSU_CR_DEVICE_ID 0

/******************************************************************/

/* Definitions for peripheral PSU_CRF_APB */
#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000
#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF


/******************************************************************/

/* Canonical definitions for peripheral PSU_CR_0 */
#define XPAR_XCRPSU_0_DEVICE_ID 0

/******************************************************************/


/* Definitions for peripheral PSU_PMU_IOMODULE */
#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000
#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF


/* Definitions for peripheral PSU_LPD_SLCR */
#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000
#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF


/******************************************************************/

/* Definitions for driver RTCPSU */
#define XPAR_XRTCPSU_NUM_INSTANCES 1

/* Definitions for peripheral PSU_RTC */
#define XPAR_PSU_RTC_DEVICE_ID 0
#define XPAR_PSU_RTC_BASEADDR 0xFFA60000
#define XPAR_PSU_RTC_HIGHADDR 0xFFA6FFFF


/******************************************************************/

/* Canonical definitions for peripheral PSU_RTC */
#define XPAR_XRTCPSU_0_DEVICE_ID XPAR_PSU_RTC_DEVICE_ID
#define XPAR_XRTCPSU_0_BASEADDR 0xFFA60000
#define XPAR_XRTCPSU_0_HIGHADDR 0xFFA6FFFF


/******************************************************************/

/* Definitions for Fabric interrupts connected to psu_rcpu_gic */
#define XPAR_FABRIC_AXI_INTC_0_IRQ_INTR 121U

/******************************************************************/

/* Canonical definitions for Fabric interrupts connected to psu_rcpu_gic */
#define XPAR_FABRIC_INTC_0_VEC_ID XPAR_FABRIC_AXI_INTC_0_IRQ_INTR

/******************************************************************/

/* Definitions for driver SCUGIC */
#define XPAR_XSCUGIC_NUM_INSTANCES 1U

/* Definitions for peripheral PSU_RCPU_GIC */
#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0U
#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000U
#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFFU
#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000U


/******************************************************************/

/* Canonical definitions for peripheral PSU_RCPU_GIC */
#define XPAR_SCUGIC_0_DEVICE_ID 0U
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000U
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFFU
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000U


/******************************************************************/

/* Definitions for driver SDPS */
#define XPAR_XSDPS_NUM_INSTANCES 2

/* Definitions for peripheral PSU_SD_0 */
#define XPAR_PSU_SD_0_DEVICE_ID 0
#define XPAR_PSU_SD_0_BASEADDR 0xFF160000
#define XPAR_PSU_SD_0_HIGHADDR 0xFF16FFFF
#define XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ 187500000
#define XPAR_PSU_SD_0_HAS_CD 1
#define XPAR_PSU_SD_0_HAS_WP 0
#define XPAR_PSU_SD_0_BUS_WIDTH 4
#define XPAR_PSU_SD_0_MIO_BANK 0
#define XPAR_PSU_SD_0_HAS_EMIO 0


/* Definitions for peripheral PSU_SD_1 */
#define XPAR_PSU_SD_1_DEVICE_ID 1
#define XPAR_PSU_SD_1_BASEADDR 0xFF170000
#define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF
#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 187500000
#define XPAR_PSU_SD_1_HAS_CD 0
#define XPAR_PSU_SD_1_HAS_WP 0
#define XPAR_PSU_SD_1_BUS_WIDTH 4
#define XPAR_PSU_SD_1_MIO_BANK 1
#define XPAR_PSU_SD_1_HAS_EMIO 0


/******************************************************************/

#define XPAR_PSU_SD_0_IS_CACHE_COHERENT 0
#define XPAR_PSU_SD_0_REF_CLK 0xff
#define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0
#define XPAR_PSU_SD_1_REF_CLK 0xff
/* Canonical definitions for peripheral PSU_SD_0 */
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_0_DEVICE_ID
#define XPAR_XSDPS_0_BASEADDR 0xFF160000
#define XPAR_XSDPS_0_HIGHADDR 0xFF16FFFF
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 187500000
#define XPAR_XSDPS_0_HAS_CD 1
#define XPAR_XSDPS_0_HAS_WP 0
#define XPAR_XSDPS_0_BUS_WIDTH 4
#define XPAR_XSDPS_0_MIO_BANK 0
#define XPAR_XSDPS_0_HAS_EMIO 0
#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0

/* Canonical definitions for peripheral PSU_SD_1 */
#define XPAR_XSDPS_1_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID
#define XPAR_XSDPS_1_BASEADDR 0xFF170000
#define XPAR_XSDPS_1_HIGHADDR 0xFF17FFFF
#define XPAR_XSDPS_1_SDIO_CLK_FREQ_HZ 187500000
#define XPAR_XSDPS_1_HAS_CD 0
#define XPAR_XSDPS_1_HAS_WP 0
#define XPAR_XSDPS_1_BUS_WIDTH 4
#define XPAR_XSDPS_1_MIO_BANK 1
#define XPAR_XSDPS_1_HAS_EMIO 0
#define XPAR_XSDPS_1_IS_CACHE_COHERENT 0


/******************************************************************/

/* Definitions for driver SPIPS */
#define XPAR_XSPIPS_NUM_INSTANCES 2

/* Definitions for peripheral PSU_SPI_0 */
#define XPAR_PSU_SPI_0_DEVICE_ID 0
#define XPAR_PSU_SPI_0_BASEADDR 0xFF040000
#define XPAR_PSU_SPI_0_HIGHADDR 0xFF04FFFF
#define XPAR_PSU_SPI_0_SPI_CLK_FREQ_HZ 187500000


/* Definitions for peripheral PSU_SPI_1 */
#define XPAR_PSU_SPI_1_DEVICE_ID 1
#define XPAR_PSU_SPI_1_BASEADDR 0xFF050000
#define XPAR_PSU_SPI_1_HIGHADDR 0xFF05FFFF
#define XPAR_PSU_SPI_1_SPI_CLK_FREQ_HZ 187500000


/******************************************************************/

/* Canonical definitions for peripheral PSU_SPI_0 */
#define XPAR_XSPIPS_0_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID
#define XPAR_XSPIPS_0_BASEADDR 0xFF040000
#define XPAR_XSPIPS_0_HIGHADDR 0xFF04FFFF
#define XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ 187500000

/* Canonical definitions for peripheral PSU_SPI_1 */
#define XPAR_XSPIPS_1_DEVICE_ID XPAR_PSU_SPI_1_DEVICE_ID
#define XPAR_XSPIPS_1_BASEADDR 0xFF050000
#define XPAR_XSPIPS_1_HIGHADDR 0xFF05FFFF
#define XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ 187500000


/******************************************************************/

/* Definitions for driver SYSMONPSU */
#define XPAR_XSYSMONPSU_NUM_INSTANCES 1

/* Definitions for peripheral PSU_AMS */
#define XPAR_PSU_AMS_DEVICE_ID 0
#define XPAR_PSU_AMS_BASEADDR 0xFFA50000
#define XPAR_PSU_AMS_HIGHADDR 0xFFA5FFFF


/******************************************************************/

#define XPAR_PSU_AMS_REF_FREQMHZ 51.724136
/* Canonical definitions for peripheral PSU_AMS */
#define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID
#define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000
#define XPAR_XSYSMONPSU_0_HIGHADDR 0xFFA5FFFF


/******************************************************************/

#define XPAR_XSYSMONPSU_0_REF_FREQMHZ 51.724136
/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1U

/* Definitions for peripheral AXI_TIMER_0 */
#define XPAR_AXI_TIMER_0_DEVICE_ID 0U
#define XPAR_AXI_TIMER_0_BASEADDR 0x80010000U
#define XPAR_AXI_TIMER_0_HIGHADDR 0x8001FFFFU
#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000U


/******************************************************************/

/* Canonical definitions for peripheral AXI_TIMER_0 */
#define XPAR_TMRCTR_0_DEVICE_ID 0U
#define XPAR_TMRCTR_0_BASEADDR 0x80010000U
#define XPAR_TMRCTR_0_HIGHADDR 0x8001FFFFU
#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ

/******************************************************************/

/* Definitions for driver TTCPS */
#define XPAR_XTTCPS_NUM_INSTANCES 12U

/* Definitions for peripheral PSU_TTC_0 */
#define XPAR_PSU_TTC_0_DEVICE_ID 0U
#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000U
#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0U
#define XPAR_PSU_TTC_1_DEVICE_ID 1U
#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004U
#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0U
#define XPAR_PSU_TTC_2_DEVICE_ID 2U
#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008U
#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0U


/* Definitions for peripheral PSU_TTC_1 */
#define XPAR_PSU_TTC_3_DEVICE_ID 3U
#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000U
#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0U
#define XPAR_PSU_TTC_4_DEVICE_ID 4U
#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004U
#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0U
#define XPAR_PSU_TTC_5_DEVICE_ID 5U
#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008U
#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0U


/* Definitions for peripheral PSU_TTC_2 */
#define XPAR_PSU_TTC_6_DEVICE_ID 6U
#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000U
#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0U
#define XPAR_PSU_TTC_7_DEVICE_ID 7U
#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004U
#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0U
#define XPAR_PSU_TTC_8_DEVICE_ID 8U
#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008U
#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0U


/* Definitions for peripheral PSU_TTC_3 */
#define XPAR_PSU_TTC_9_DEVICE_ID 9U
#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000U
#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0U
#define XPAR_PSU_TTC_10_DEVICE_ID 10U
#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004U
#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0U
#define XPAR_PSU_TTC_11_DEVICE_ID 11U
#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008U
#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0U


/******************************************************************/

/* Canonical definitions for peripheral PSU_TTC_0 */
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID
#define XPAR_XTTCPS_0_BASEADDR 0xFF110000U
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID
#define XPAR_XTTCPS_1_BASEADDR 0xFF110004U
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID
#define XPAR_XTTCPS_2_BASEADDR 0xFF110008U
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U

/* Canonical definitions for peripheral PSU_TTC_1 */
#define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID
#define XPAR_XTTCPS_3_BASEADDR 0xFF120000U
#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID
#define XPAR_XTTCPS_4_BASEADDR 0xFF120004U
#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID
#define XPAR_XTTCPS_5_BASEADDR 0xFF120008U
#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0U

/* Canonical definitions for peripheral PSU_TTC_2 */
#define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID
#define XPAR_XTTCPS_6_BASEADDR 0xFF130000U
#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID
#define XPAR_XTTCPS_7_BASEADDR 0xFF130004U
#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID
#define XPAR_XTTCPS_8_BASEADDR 0xFF130008U
#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0U

/* Canonical definitions for peripheral PSU_TTC_3 */
#define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID
#define XPAR_XTTCPS_9_BASEADDR 0xFF140000U
#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID
#define XPAR_XTTCPS_10_BASEADDR 0xFF140004U
#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID
#define XPAR_XTTCPS_11_BASEADDR 0xFF140008U
#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000U
#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0U


/******************************************************************/

/* Definitions for driver UARTPS */
#define XPAR_XUARTPS_NUM_INSTANCES 2

/* Definitions for peripheral PSU_UART_0 */
#define XPAR_PSU_UART_0_DEVICE_ID 0
#define XPAR_PSU_UART_0_BASEADDR 0xFF000000
#define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF
#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 100000000
#define XPAR_PSU_UART_0_HAS_MODEM 0


/* Definitions for peripheral PSU_UART_1 */
#define XPAR_PSU_UART_1_DEVICE_ID 1
#define XPAR_PSU_UART_1_BASEADDR 0xFF010000
#define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF
#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 100000000
#define XPAR_PSU_UART_1_HAS_MODEM 0


/******************************************************************/

/* Canonical definitions for peripheral PSU_UART_0 */
#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID
#define XPAR_XUARTPS_0_BASEADDR 0xFF000000
#define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF
#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
#define XPAR_XUARTPS_0_HAS_MODEM 0

/* Canonical definitions for peripheral PSU_UART_1 */
#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID
#define XPAR_XUARTPS_1_BASEADDR 0xFF010000
#define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF
#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 100000000
#define XPAR_XUARTPS_1_HAS_MODEM 0


/******************************************************************/

/* Definition for input Clock */
#define XPAR_PSU_UART_0_REF_CLK UART0_REF
/* Definition for input Clock */
#define XPAR_PSU_UART_1_REF_CLK UART1_REF
/* Definitions for driver USBPSU */
#define XPAR_XUSBPSU_NUM_INSTANCES 2

/* Definitions for peripheral PSU_USB_XHCI_0 */
#define XPAR_PSU_USB_XHCI_0_DEVICE_ID 0
#define XPAR_PSU_USB_XHCI_0_BASEADDR 0xFE200000
#define XPAR_PSU_USB_XHCI_0_HIGHADDR 0xFE20FFFF


/* Definitions for peripheral PSU_USB_XHCI_1 */
#define XPAR_PSU_USB_XHCI_1_DEVICE_ID 1
#define XPAR_PSU_USB_XHCI_1_BASEADDR 0xFE300000
#define XPAR_PSU_USB_XHCI_1_HIGHADDR 0xFE30FFFF


/******************************************************************/

#define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0
#define XPAR_PSU_USB_XHCI_0_REF_CLK 0xff
#define XPAR_PSU_USB_XHCI_0_SUPER_SPEED 1
#define XPAR_PSU_USB_XHCI_1_IS_CACHE_COHERENT 0
#define XPAR_PSU_USB_XHCI_1_REF_CLK 0xff
#define XPAR_PSU_USB_XHCI_1_SUPER_SPEED 1
/* Canonical definitions for peripheral PSU_USB_XHCI_0 */
#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID
#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000
#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF

/* Canonical definitions for peripheral PSU_USB_XHCI_1 */
#define XPAR_XUSBPSU_1_DEVICE_ID XPAR_PSU_USB_XHCI_1_DEVICE_ID
#define XPAR_XUSBPSU_1_BASEADDR 0xFE300000
#define XPAR_XUSBPSU_1_HIGHADDR 0xFE30FFFF


/******************************************************************/

/* Definitions for driver WDTPS */
#define XPAR_XWDTPS_NUM_INSTANCES 3

/* Definitions for peripheral PSU_CSU_WDT */
#define XPAR_PSU_CSU_WDT_DEVICE_ID 0
#define XPAR_PSU_CSU_WDT_BASEADDR 0xFFCB0000
#define XPAR_PSU_CSU_WDT_HIGHADDR 0xFFCBFFFF
#define XPAR_PSU_CSU_WDT_WDT_CLK_FREQ_HZ 100000000


/* Definitions for peripheral PSU_WDT_0 */
#define XPAR_PSU_WDT_0_DEVICE_ID 1
#define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
#define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 100000000


/* Definitions for peripheral PSU_WDT_1 */
#define XPAR_PSU_WDT_1_DEVICE_ID 2
#define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
#define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 100000000


/******************************************************************/

/* Canonical definitions for peripheral PSU_CSU_WDT */
#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_CSU_WDT_DEVICE_ID
#define XPAR_XWDTPS_0_BASEADDR 0xFFCB0000
#define XPAR_XWDTPS_0_HIGHADDR 0xFFCBFFFF
#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 100000000

/* Canonical definitions for peripheral PSU_WDT_0 */
#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
#define XPAR_XWDTPS_1_BASEADDR 0xFF150000
#define XPAR_XWDTPS_1_HIGHADDR 0xFF15FFFF
#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 100000000

/* Canonical definitions for peripheral PSU_WDT_1 */
#define XPAR_XWDTPS_2_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
#define XPAR_XWDTPS_2_BASEADDR 0xFD4D0000
#define XPAR_XWDTPS_2_HIGHADDR 0xFD4DFFFF
#define XPAR_XWDTPS_2_WDT_CLK_FREQ_HZ 100000000


/******************************************************************/

/* Definitions for driver ZDMA */
#define XPAR_XZDMA_NUM_INSTANCES 16

/* Definitions for peripheral PSU_ADMA_0 */
#define XPAR_PSU_ADMA_0_DEVICE_ID 0
#define XPAR_PSU_ADMA_0_BASEADDR 0xFFA80000
#define XPAR_PSU_ADMA_0_DMA_MODE 1
#define XPAR_PSU_ADMA_0_HIGHADDR 0xFFA8FFFF
#define XPAR_PSU_ADMA_0_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_ADMA_1 */
#define XPAR_PSU_ADMA_1_DEVICE_ID 1
#define XPAR_PSU_ADMA_1_BASEADDR 0xFFA90000
#define XPAR_PSU_ADMA_1_DMA_MODE 1
#define XPAR_PSU_ADMA_1_HIGHADDR 0xFFA9FFFF
#define XPAR_PSU_ADMA_1_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_ADMA_2 */
#define XPAR_PSU_ADMA_2_DEVICE_ID 2
#define XPAR_PSU_ADMA_2_BASEADDR 0xFFAA0000
#define XPAR_PSU_ADMA_2_DMA_MODE 1
#define XPAR_PSU_ADMA_2_HIGHADDR 0xFFAAFFFF
#define XPAR_PSU_ADMA_2_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_ADMA_3 */
#define XPAR_PSU_ADMA_3_DEVICE_ID 3
#define XPAR_PSU_ADMA_3_BASEADDR 0xFFAB0000
#define XPAR_PSU_ADMA_3_DMA_MODE 1
#define XPAR_PSU_ADMA_3_HIGHADDR 0xFFABFFFF
#define XPAR_PSU_ADMA_3_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_ADMA_4 */
#define XPAR_PSU_ADMA_4_DEVICE_ID 4
#define XPAR_PSU_ADMA_4_BASEADDR 0xFFAC0000
#define XPAR_PSU_ADMA_4_DMA_MODE 1
#define XPAR_PSU_ADMA_4_HIGHADDR 0xFFACFFFF
#define XPAR_PSU_ADMA_4_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_ADMA_5 */
#define XPAR_PSU_ADMA_5_DEVICE_ID 5
#define XPAR_PSU_ADMA_5_BASEADDR 0xFFAD0000
#define XPAR_PSU_ADMA_5_DMA_MODE 1
#define XPAR_PSU_ADMA_5_HIGHADDR 0xFFADFFFF
#define XPAR_PSU_ADMA_5_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_ADMA_6 */
#define XPAR_PSU_ADMA_6_DEVICE_ID 6
#define XPAR_PSU_ADMA_6_BASEADDR 0xFFAE0000
#define XPAR_PSU_ADMA_6_DMA_MODE 1
#define XPAR_PSU_ADMA_6_HIGHADDR 0xFFAEFFFF
#define XPAR_PSU_ADMA_6_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_ADMA_7 */
#define XPAR_PSU_ADMA_7_DEVICE_ID 7
#define XPAR_PSU_ADMA_7_BASEADDR 0xFFAF0000
#define XPAR_PSU_ADMA_7_DMA_MODE 1
#define XPAR_PSU_ADMA_7_HIGHADDR 0xFFAFFFFF
#define XPAR_PSU_ADMA_7_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_GDMA_0 */
#define XPAR_PSU_GDMA_0_DEVICE_ID 8
#define XPAR_PSU_GDMA_0_BASEADDR 0xFD500000
#define XPAR_PSU_GDMA_0_DMA_MODE 0
#define XPAR_PSU_GDMA_0_HIGHADDR 0xFD50FFFF
#define XPAR_PSU_GDMA_0_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_GDMA_1 */
#define XPAR_PSU_GDMA_1_DEVICE_ID 9
#define XPAR_PSU_GDMA_1_BASEADDR 0xFD510000
#define XPAR_PSU_GDMA_1_DMA_MODE 0
#define XPAR_PSU_GDMA_1_HIGHADDR 0xFD51FFFF
#define XPAR_PSU_GDMA_1_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_GDMA_2 */
#define XPAR_PSU_GDMA_2_DEVICE_ID 10
#define XPAR_PSU_GDMA_2_BASEADDR 0xFD520000
#define XPAR_PSU_GDMA_2_DMA_MODE 0
#define XPAR_PSU_GDMA_2_HIGHADDR 0xFD52FFFF
#define XPAR_PSU_GDMA_2_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_GDMA_3 */
#define XPAR_PSU_GDMA_3_DEVICE_ID 11
#define XPAR_PSU_GDMA_3_BASEADDR 0xFD530000
#define XPAR_PSU_GDMA_3_DMA_MODE 0
#define XPAR_PSU_GDMA_3_HIGHADDR 0xFD53FFFF
#define XPAR_PSU_GDMA_3_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_GDMA_4 */
#define XPAR_PSU_GDMA_4_DEVICE_ID 12
#define XPAR_PSU_GDMA_4_BASEADDR 0xFD540000
#define XPAR_PSU_GDMA_4_DMA_MODE 0
#define XPAR_PSU_GDMA_4_HIGHADDR 0xFD54FFFF
#define XPAR_PSU_GDMA_4_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_GDMA_5 */
#define XPAR_PSU_GDMA_5_DEVICE_ID 13
#define XPAR_PSU_GDMA_5_BASEADDR 0xFD550000
#define XPAR_PSU_GDMA_5_DMA_MODE 0
#define XPAR_PSU_GDMA_5_HIGHADDR 0xFD55FFFF
#define XPAR_PSU_GDMA_5_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_GDMA_6 */
#define XPAR_PSU_GDMA_6_DEVICE_ID 14
#define XPAR_PSU_GDMA_6_BASEADDR 0xFD560000
#define XPAR_PSU_GDMA_6_DMA_MODE 0
#define XPAR_PSU_GDMA_6_HIGHADDR 0xFD56FFFF
#define XPAR_PSU_GDMA_6_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSU_GDMA_7 */
#define XPAR_PSU_GDMA_7_DEVICE_ID 15
#define XPAR_PSU_GDMA_7_BASEADDR 0xFD570000
#define XPAR_PSU_GDMA_7_DMA_MODE 0
#define XPAR_PSU_GDMA_7_HIGHADDR 0xFD57FFFF
#define XPAR_PSU_GDMA_7_ZDMA_CLK_FREQ_HZ 0


/******************************************************************/

#define XPAR_PSU_ADMA_0_IS_CACHE_COHERENT 0
#define XPAR_PSU_ADMA_1_IS_CACHE_COHERENT 0
#define XPAR_PSU_ADMA_2_IS_CACHE_COHERENT 0
#define XPAR_PSU_ADMA_3_IS_CACHE_COHERENT 0
#define XPAR_PSU_ADMA_4_IS_CACHE_COHERENT 0
#define XPAR_PSU_ADMA_5_IS_CACHE_COHERENT 0
#define XPAR_PSU_ADMA_6_IS_CACHE_COHERENT 0
#define XPAR_PSU_ADMA_7_IS_CACHE_COHERENT 0
#define XPAR_PSU_GDMA_0_IS_CACHE_COHERENT 0
#define XPAR_PSU_GDMA_1_IS_CACHE_COHERENT 0
#define XPAR_PSU_GDMA_2_IS_CACHE_COHERENT 0
#define XPAR_PSU_GDMA_3_IS_CACHE_COHERENT 0
#define XPAR_PSU_GDMA_4_IS_CACHE_COHERENT 0
#define XPAR_PSU_GDMA_5_IS_CACHE_COHERENT 0
#define XPAR_PSU_GDMA_6_IS_CACHE_COHERENT 0
#define XPAR_PSU_GDMA_7_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral PSU_ADMA_0 */
#define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID
#define XPAR_XZDMA_0_BASEADDR 0xFFA80000
#define XPAR_XZDMA_0_DMA_MODE 1
#define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF
#define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_ADMA_1 */
#define XPAR_XZDMA_1_DEVICE_ID XPAR_PSU_ADMA_1_DEVICE_ID
#define XPAR_XZDMA_1_BASEADDR 0xFFA90000
#define XPAR_XZDMA_1_DMA_MODE 1
#define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF
#define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_ADMA_2 */
#define XPAR_XZDMA_2_DEVICE_ID XPAR_PSU_ADMA_2_DEVICE_ID
#define XPAR_XZDMA_2_BASEADDR 0xFFAA0000
#define XPAR_XZDMA_2_DMA_MODE 1
#define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF
#define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_ADMA_3 */
#define XPAR_XZDMA_3_DEVICE_ID XPAR_PSU_ADMA_3_DEVICE_ID
#define XPAR_XZDMA_3_BASEADDR 0xFFAB0000
#define XPAR_XZDMA_3_DMA_MODE 1
#define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF
#define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_ADMA_4 */
#define XPAR_XZDMA_4_DEVICE_ID XPAR_PSU_ADMA_4_DEVICE_ID
#define XPAR_XZDMA_4_BASEADDR 0xFFAC0000
#define XPAR_XZDMA_4_DMA_MODE 1
#define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF
#define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_ADMA_5 */
#define XPAR_XZDMA_5_DEVICE_ID XPAR_PSU_ADMA_5_DEVICE_ID
#define XPAR_XZDMA_5_BASEADDR 0xFFAD0000
#define XPAR_XZDMA_5_DMA_MODE 1
#define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF
#define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_ADMA_6 */
#define XPAR_XZDMA_6_DEVICE_ID XPAR_PSU_ADMA_6_DEVICE_ID
#define XPAR_XZDMA_6_BASEADDR 0xFFAE0000
#define XPAR_XZDMA_6_DMA_MODE 1
#define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF
#define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_ADMA_7 */
#define XPAR_XZDMA_7_DEVICE_ID XPAR_PSU_ADMA_7_DEVICE_ID
#define XPAR_XZDMA_7_BASEADDR 0xFFAF0000
#define XPAR_XZDMA_7_DMA_MODE 1
#define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF
#define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_GDMA_0 */
#define XPAR_XZDMA_8_DEVICE_ID XPAR_PSU_GDMA_0_DEVICE_ID
#define XPAR_XZDMA_8_BASEADDR 0xFD500000
#define XPAR_XZDMA_8_DMA_MODE 0
#define XPAR_XZDMA_8_HIGHADDR 0xFD50FFFF
#define XPAR_XZDMA_8_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_GDMA_1 */
#define XPAR_XZDMA_9_DEVICE_ID XPAR_PSU_GDMA_1_DEVICE_ID
#define XPAR_XZDMA_9_BASEADDR 0xFD510000
#define XPAR_XZDMA_9_DMA_MODE 0
#define XPAR_XZDMA_9_HIGHADDR 0xFD51FFFF
#define XPAR_XZDMA_9_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_GDMA_2 */
#define XPAR_XZDMA_10_DEVICE_ID XPAR_PSU_GDMA_2_DEVICE_ID
#define XPAR_XZDMA_10_BASEADDR 0xFD520000
#define XPAR_XZDMA_10_DMA_MODE 0
#define XPAR_XZDMA_10_HIGHADDR 0xFD52FFFF
#define XPAR_XZDMA_10_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_GDMA_3 */
#define XPAR_XZDMA_11_DEVICE_ID XPAR_PSU_GDMA_3_DEVICE_ID
#define XPAR_XZDMA_11_BASEADDR 0xFD530000
#define XPAR_XZDMA_11_DMA_MODE 0
#define XPAR_XZDMA_11_HIGHADDR 0xFD53FFFF
#define XPAR_XZDMA_11_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_GDMA_4 */
#define XPAR_XZDMA_12_DEVICE_ID XPAR_PSU_GDMA_4_DEVICE_ID
#define XPAR_XZDMA_12_BASEADDR 0xFD540000
#define XPAR_XZDMA_12_DMA_MODE 0
#define XPAR_XZDMA_12_HIGHADDR 0xFD54FFFF
#define XPAR_XZDMA_12_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_GDMA_5 */
#define XPAR_XZDMA_13_DEVICE_ID XPAR_PSU_GDMA_5_DEVICE_ID
#define XPAR_XZDMA_13_BASEADDR 0xFD550000
#define XPAR_XZDMA_13_DMA_MODE 0
#define XPAR_XZDMA_13_HIGHADDR 0xFD55FFFF
#define XPAR_XZDMA_13_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_GDMA_6 */
#define XPAR_XZDMA_14_DEVICE_ID XPAR_PSU_GDMA_6_DEVICE_ID
#define XPAR_XZDMA_14_BASEADDR 0xFD560000
#define XPAR_XZDMA_14_DMA_MODE 0
#define XPAR_XZDMA_14_HIGHADDR 0xFD56FFFF
#define XPAR_XZDMA_14_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSU_GDMA_7 */
#define XPAR_XZDMA_15_DEVICE_ID XPAR_PSU_GDMA_7_DEVICE_ID
#define XPAR_XZDMA_15_BASEADDR 0xFD570000
#define XPAR_XZDMA_15_DMA_MODE 0
#define XPAR_XZDMA_15_HIGHADDR 0xFD57FFFF
#define XPAR_XZDMA_15_ZDMA_CLK_FREQ_HZ 0


/******************************************************************/

#endif  /* end of protection macro */

Edit to add: in the GIC version of the hardware platform, I do see the XPAR_FABRIC_AXI_TIMER_0_INTERRUPT_INTR in the xparameters.h, and its value there is 121U.