I'm trying to develop a RISC-V processor in Verilog and SystemVerilog and then later want to synthesize and test it on FPGA. I'm currently using Xilinx Vivado to write and debug code. But, the issue which I'm facing is that as my processor is scaling up it is very hard to debug. The step execution in Vivado is very itritative and doesn't display the values of different instantiated modules at the same time. I just wanted to know if there is any other better software to do the job which is easier to debug, provides a visual representation of the design, displays the variable values at each step etc.
Thank you for reading my question, I'm looking forward to get some valuable response.
