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Issues with outputs on new ZCU104 eval kit

Akropolidis

I just obtained a new ZCU104 Eval kit (AMD Zynq Ultrascale+ MPSoC ZCU104 Evaluation Kit) and I'm running into some issues with my bitstreams.

 

I have a bitstream implementation of a ARM Cortex-M0 mcu and tested this on the board and observed the expected results. Now I want to move development to another ZCU104 eval board that I've just obtained, I flashed the exact bitstream but the I/Os don't seem to be working. In debugging, I tested with a simpler design below:

  1. `timescale 1ns/1ps
  2.  
  3. module test(
  4. input logic clk_p,
  5. input logic clk_n,
  6. output logic clk_50,
  7. // output logic sys_clk,
  8. // output logic locked,
  9. output logic [2:0] led
  10. );
  11.  
  12. logic sys_clk;
  13. logic locked;
  14.  
  15. IBUFGDS osc_clk (
  16. .O(sys_clk),
  17. .I(clk_p),
  18. .IB(clk_n)
  19. );
  20.  
  21. clk_wiz_1 clock_test
  22. (
  23. // Clock out ports
  24. .clk_out1(clk_50), // output clk_out1
  25. // Status and control signals
  26. .locked(locked), // output locked
  27. // Clock in ports
  28. .clk_in1(sys_clk) // input clk_in1
  29. );
  30.  
  31. assign led[0] = locked;
  32. assign led[1] = 1'b1;
  33. assign led[2] = 1'b1;
  34.  
  35. endmodule

  1. # Clock - ZCU104 125MHz System Clock (Differential)
  2. set_property PACKAGE_PIN F23 [get_ports clk_p]
  3. set_property IOSTANDARD LVDS [get_ports clk_p]
  4. set_property PACKAGE_PIN E23 [get_ports clk_n]
  5. set_property IOSTANDARD LVDS [get_ports clk_n]
  6.  
  7. ##############################################################
  8. # Status LEDs - ZCU104 User LEDs
  9. ##############################################################
  10.  
  11. set_property PACKAGE_PIN D6 [get_ports clk_50]
  12. set_property IOSTANDARD LVCMOS33 [get_ports clk_50]
  13.  
  14. set_property PACKAGE_PIN D5 [get_ports {led[0]}]
  15. set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
  16.  
  17. set_property PACKAGE_PIN A5 [get_ports {led[1]}]
  18. set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
  19.  
  20. set_property PACKAGE_PIN B5 [get_ports {led[2]}]
  21. set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]

What's interesting is I did observe an expected output from driving the pins of the led directly with assign statements as shown above. But the led connected to locked which is an output driven by the clock wiz module is not set. Running post synthesis and implementation simulations indicate the locked signal and clock wizard work fine so I'm confused.

 

I think the issue is in the hardware configuration, are there additional bringup steps that I'm missing? I've referenced the documentation and SW6 is set to JTAG mode (0000/0x0) but I can't seem to find the issue.