I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

Question

I&rsquo;m running into a recurring problem with Zynq designs and I&rsquo;m curious how others handle this. 
 On paper, using the PL for acceleration always looks like the right move. In practice, I keep finding that the integration cost &mdash;AXI plumbing, cache coherency, DMA setup, and tool friction&mdash;ends up dominating the project far more than the accelerator itself. 
 I&rsquo;ve had projects where the hardware worked, but performance was still disappointing because the PS&ndash;PL interface became the bottleneck, or where workflow choices (Vivado vs Vitis) boxed me into painful rework later. 
 So my question is: at what point do you personally decide that moving functionality into the PL is worth it on Zynq, and when do you step back and keep things in software instead? 
 I&rsquo;d really like to hear what decision signals or failure experiences others use to make that call.

venkat01 · Accepted Answer

Well, I mostly deal with the designs targeting the PL only and I prefer using Microblaze instead of the PS, power profile and the latency are the key factors for the designs in my line of work. 
 For resolving the latency issues it's preferable to move onto the US/US+ MPSoC's , the throughput over the PS-PL bridge is much better with min optimisations.

wolfgangfriedrich · Answer

The only way to win the performance game is, when the data is entering the PL side directly from external sources. I have fast ADCs connected straight to the PL through QSPI, do the expensive filtering in the PL side and the pipe it through a AXI-FIFO to the PS side for storage. 
 As you said, moving data PS -> PL -> processing -> PS is not efficient.

I’m running into a recurring problem with Zynq designs and I’m curious how others handle this.

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