This article describes the proprietary technology issues I had to consider when designing Flavia, the Free Logic Array, specifically the Xilinx version. Xilinx does not fully document their FPGA bitstream formats and doesn’t want anyone reverse-engineering them and publishing the results. However, they do provide a documented way to locate LUTs and FFs for your own designs. This is all that’s needed for Flavia and doesn’t endanger the security of other Xilinx bitstreams.
After addressing Xilinx’s security concerns, I describe the FPGA design files used by Flavia’s first Xilinx implementation, FlaviaP32. This article supplements Flavia: the Free Logic Array.
