I am creating this to record my observations and readings so far. View this as an appendix of information and not a source of things.
The Ultra96-V2 Developer Kit supports the following features:
- Zynq UltraScale+ MPSoC ZU3EG SBVA484
- Storage
- Micron 2 GB (512M x32) LPDDR4 Memory
- MicroSD Socket
- Ships with Delkin Utility MLC Industrial 16GB card
- Wi-Fi / Bluetooth
- DisplayPort
- 1x USB 3.0 Type Micro-B upstream port
- 2x USB 3.0 Type A downstream ports
- 40-pin Low-speed expansion header
- 60-pin High speed expansion header
- Mounted on thermal bracket with fan
Note: There is no on-board, wired Ethernet interface. All communications must be done via USB, Wi-Fi, JTAG, or expansion interface.
For better communications, get a USB to Ethernet adaptor!
The Master Memory Interface
The master memory interface uses the AXI Coherency Extension (ACE) protocol to communicate with the Cache Coherent Interconnect (CCI).
Previously, the Cortex-A9 application processor in the Zynq So C used AXI to communicate between processing elements throughout the device [14].
The Cortex-A53 application processor in the Zynq MPSoC uses ACE, which is part of the AMBA open standard (described i n Section 3.5.1).
The ACE protocol is similar to AXI, however, supports hardware coherency. This allows for system-level communication of up-to-date and information across the entire Zynq MPSoC.
A concept known as barrier transactions is used in the ACE protocol to manage the order of transactions efficiently. A barrier transaction is where the ACE protocol stalls the processing flow of data until a particular condition has been met [1]. There are two types of barrier transaction. The first is a memory barrier, which is used to ensure that transactions issued before the barrier are fully completed before transactions that are issued after the barrier. The memory barrier could be used to make sure that data has been successfully written to a memory location before another master initiates a read operation on the same memory space. The other type of barrier transaction is a synchronisation barrier, which prevents all master devices in a system from issuing a transaction until all previous transactions have successfully resolved.
Barrier transactions are possible using ACE since there are additional control signals added to the existing read address, read data, write address and write data channels of the AXI protocol. These allow for barrier signalling between components and indicate which masters should manage the barrier transactions. There are also additional signals for snooping which indicate the type of snoop (read or write) to be carried out [1].
Snooping is a major factor in achieving coherency between the APU and the remaining Zynq MPSo C components. Coherency relies on all master devices listening to every transaction issued by other masters . Upon a read operation being carried out, the master device with the most current data will provide it to the requesting master. Similarly, when a write operation is detected, the local copy held by the master ‘listening in’ will be invalidated [2]. Snooping makes it is possible to achieve coherency and ensures write operations to the same memory location are discernible by two or more master devices.
So I discovered the cryptography capabilities of this cool board:
and also
Zynq UltraScale+ devices use a hardened AES cryptographic block for AES encryption and decryption.
The AES cryptographic block accepts keys from several sources. The 256-bit eFUSE AES key is stored either in the BBRAM or eFUSEs.
The AES key can also be stored in an obfuscated or black format in external eFUSE. Unlike in Xilinx 7 series FPGAs and Zynq-7000 devices, the AES key cannot be read after it is programmed. The value of the key can be verified. The Zynq UltraScale+ device also supports AES cryptographic functions using the physically uncloneable function (PUF), as discussed in PUF Support. In one of the two modes which use the PUF, eFUSEs are used.
