Simple Electronic DC Load Conditional Oscillations

Question

I have recently completed a build of a simple DC electronic load with the specifications of 1 mA to 2000 ma and up to 55 Volts as long as total power is kept below 60 Watts. I will be blogging about this build in the coming days.

During the prototyping phase of the project I had no problems with oscillations but moving the design to a circuit board always has the potential to change things. In this case I find that the unit works properly if I bring up the load from a low current to the desired level or if I bring the voltage applied to the load from a low level up to the desired voltage. If however I have the load set for any value over 250 mA and then apply a voltage above 6 volts I will get an oscillation that is undesirable. Once the unit is powered and free of oscillation I am able to move the voltage to any level and the load to any level without any recurrence of the oscillation. It seems that it is just the initial impact of full voltage into a previously set load that is greater than 250 mA that triggers the oscillation.

Now it is very possible that the design that I have used, which has a general traditional layout with my own modifications frankensteined into it, is bad. Since I am not an engineer I can do things like this but if I fail then I need the engineers to help me clean up my mess. Here is a schematic of the project and any insights on how I can make the unit oscillation proof will be welcome.

Since this is just a tool for my own shop I can live with the oscillation anomaly as the power or the load can just routinely be brought together gently but aesthetically it would be nice if it didn't have to be babied.

Thanks John

hlipka · Accepted Answer

Things to notice:

the LT1006 is not a rail-to-rail opamp. With 5V suppy its output goes up to between 4.0 and 4.4V (best case), depending on the load, which is not enough to ensure the IRF234 is fully open (its threshold voltage is 4.0V worst case). You should increase the supply voltage
C4 is probably too big, and to be effective as a filter it would need a resistor between its + pin and the sense resistor anyway. Remove it, or reduce its value (low nF)
the FET gate resistor is probably too big, this reduces the slew rate of the gate and slows down response
what is the purpose of R6? Having it in this place means that any changes in the ground current of the opamp will change the ground reference voltage - and this happens when the FET is turned on or off. Remove it (actually I would guess that this is causing the oscillations)
you might need an additional, larger, decoupling cap for the LT1006 because it eneds to drive the FET gate which can involve larger currents

The LT1006 seems to be a quite slow opamp (its data sheet does not even state a GBW figure, but the output slew rate is quite low), so it should not oscillate. The usual remedy for oscillations is a small capacitor (below several tens of pF) beween the opamp output and the negative input (or a R-C-combination of about 1k+1nF).

hlipka · Answer

Using a R2R-Opamp only solves part of the problem. When looking at the data sheet for the IRF234, especially at the diagram 'drain current vs. gate voltage', you see that even at 5V gate voltage only 1A of drain current is guaranteed. Getting more means you are lucky with the actual FET. Adding R6 also does not help in getting a higher gate voltage for the FET, it actually reduces the gate-to-source voltage a little bit. Regarding the now-worse oscillations: probably your R2R-opamp has a higher bandwidth, so it tends to oscillate easier due to the capacitive load the gate of the FET poses. Reducing R4 a little bit (the usual value here is about 10-20 ohm), and adding some (RC) feedback between output and negative input of U2 should help. When you want to know more, there is a quite extensive posting a EEVBlog outlining the simulation process to check whether the load is stable or not: https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/ . Also, jc2048 did a series of posts about electronic load stability .

hlipka · Answer

I cannot see the image (and directly using its URL says 'no permission').
One change that happens between a breadboard and a PCB is that on a breadboard usually the parasitic capacities are higher. This means you can have some dampening in the feedback that is then missing on the PCB.

jw0752 · Answer

Hi Razvan, Thank you for the good ideas to improve the design. I will eliminate the buffer op amp and set up the resistor divider to deliver the proper voltage to pin 2 of the driver Op Amp. In this case I want 2 volts as this will give me a corresponding 2 Amp max load. R6 will be eliminated and I still have to figure out how I am going to continue to implement the changes as suggested by Hendrik and you until I understand this circuit better. Unfortunately I am now working on a solder PCB and not the bread board and changing out parts for experiments is quite a bit more difficult. I won't be able to complete the experiments until tonight but the good advice I have received gets me steadily closer to a good resolution. John

hlipka · Answer

You should remove C5. Opamps do not like capacitive loads, and the capacity posed by the gate of the FET (which easily can be 1nF - for the IRF234 its 600pF) is already quite much. Having this capacitor there increases the phase shift (since it delays the response of the FET to the opamp signal), which can lead to oscillation. As suggested by Raznvan, you can try to to add a series resistor to it (while reducing it significantly), but its best to skip it. To dampen oscillations, add a (small - 200pF or so) capacitor from the Opamp output to its negative input. The ISL28128 is a nice one, but its faster than the LT1006 you had originally. This is good since it makes the DC load react faster to load changes, but it also increases the tendency to oscillate.

jc2048 · Answer

For a large input step, the output of the op amp quickly current-limits (short circuit protection), so John is slewing the output up and down on that limit as it charges and discharges the capacitor. As it's a 2.2u 25V tant, it has an ESR of 5 or 6 ohms, so for small signals it's behaving like a very crude, badly-tuned snubber. It's not very nice from a design point of view but, curiously, it does sort of give him what he wants in that it damps down the instability enough that it doesn't oscillate. It really clobbers the response to larger signals though. I had a play with it in the simulator (which is how I know the above). The simulation doesn't actually show oscillation without the tant, but that's the difference between a model and a build for you - the phase margin in the simulation is only just over 20 degrees, so it's certainly very marginal. I didn't get very far with trying to tune snubber values [I'd need more time with the Bode plots to understand what was happening], but your resistor/cap suggestion works nicely straight off. The instabilty is at the top end - peakiness on the gain just before the response tails off. That's down to the MOSFET capacitance, so the gate resistor also plays a part and needs to be taken into account along with the cap/resistor [if your aim were to tune it for best performance rather than just slugging it]. If anyone else wants me to [from the comments I don't think you and Razvan need any help], I could go through that in more detail (with pictures!). Would be a big chunk of material here in the comments, though.

shabaz · Answer

Hi John,

Awesome project : ) Looking forward to reading about it more in your blog posts.

I'm wondering if it is caused by the combination of C4 and R6. When the system is powered up for the first time, C4 is like a short, so there is a lot of current passing through R6 (from the source of the MOSFET, through C4, and up R6, to load ground. That will cause a voltage across R6, which means the voltage to the op-amp is changing. If the load is at 1A, that means the op-amp supply voltage has changed by 0.5V, which is quite significant.

mcb1 · Answer

Way back in the days at NZ Post Office power supplies were hard to get, and therefore building our own was the most cost effective.

The designer/builder of one of our had similar instability issues, and I recall it got resolved withgenerous applications of 0.1uF caps in the right places.

I was thinking you need some across the supply of both op amps, as close as possible with short leads, and across the output as well.

I'd also add a 0.1 across C3 or at least filter the zener.

I used to have the schematic for our electronic load ... it was the same power supply effectively in reverse and heating up nichrome wire.

In those days Fets were something still to be available, and good old 2N3055 (4 of them in parallel) was the transistor of choice (although later I think we uprated)

When you get it fixed, I may have a use for it.

Cheers

Mark

jadew · Answer

Hey John, Don't know how far you've gotten with your redesign, but there are a couple of things I would change in the first one: 1). I'd get rid of the first op amp (edit: also of R2 and R3) . A 6-7k resistor, in series with the 10k pot, will make the output of the potentiometer be exactly what it is on the positive input of U2. Since C3 will still be there (hopefully a bit smaller), your set point will be much more stable than it is coming out of U1. This won't solve your problems, but it should be an improvement. 2). Get rid of R6, like the others have said, but also of C4. You want as little capacitance and filtering as possible in the feedback path. 3). If after removing R6 and C4 you're still having issues, you can try slowing down the output, so a snubber network might be in order on the output of the op amp, or you could add a small cap from the output of the op amp, before R4 to the negative input. Edit: Oups, the 6-7k resistor should be only 4.5k. Regards, Razvan

jw0752 · Answer

Hi Mark,

I have it working right now.After 6 hours and a redesigned board using a R to R Op Amp. I want to continue to test it for stability. The new build gave me even more problems with oscillations. My fix will probably not meet approval but it is the best I could come up with to get the results I was looking for. I will go into more detail tomorrow but right now it is 1:45 and I am going to crash.

John

jw0752 · Answer

Hi Hendrik, I will start a new blog about my build of the unit but before I left this one I wanted to thank you again for your insight and input. I have made most of the changes that you suggested. Here is the up to date schematic. I have gone to using a ISL 28218 Op Amp with which I have had good luck in the past. The power supply is now 12 volts. R4 is 100 Ohms but I have experimented with moving it down to 10 ohms but this didn't help with a serious oscillation. I have also removed the op amp buffer between the reference control and the driver op amp. I tried a great number of things to get the design to stop oscillating. I looked at sample schematics and applied their suggestions. Whenever a test proved promising I would push the value until I could see whether it would solve the full range 1 mA to 2000 mA. This project was difficult as I was no longer working on a bread board but the solder proto board. I even brought 3 header pins up so that tests could be run without working directly on the board. In the end the only thing that worked was a capacitor C5 between the output of the OP Amp and Ground. I started at a fairly high value and then dropped the value until I got to the point where 5 mV oscillations were beginning to show when the unit was at 2000 mA. I then went one cap size larger 2.2 uF and now I can move the load from 1 mA to 2000 mA at 2 to 30 volts without any oscillation or instability. The unit will actually track the lower amperage setting down to tenths of volts input. The problem with oscillations when higher voltage is applied to existing load setting about 250 mA has disappeared. I suspect that the 2.2 uF cap is probably a ugly fix but it acts like a shock absorber and prevent the oscillation from starting. The design is now simple and should work for my rather simple needs. If you get a chance check out my Blog on the actual build. Thanks John

jadew · Answer

John, If you add a resistor in series with the capacitor you will get the snubber network that I suggested. Its point is to load down the op amp's output at the oscillation frequency (you'll have to experiment to get the correct values), while allowing it to behave almost normally at lower slopes. Razvan

michaelkellett · Answer

Hello John, Here is an LED current driver. I've used variations of this circuit in many designs and there are hundreds of thousands of them in the field. (Mostly working OK, I guess, since the customer is still with me !). This one is a little odd since it came from a design that I can publish. The concept is very similar to Razvan's excellent suggestions. The transient response (and in extremis; stopping oscillating) is tuned by the combination of MOSFET gate rapacity, R21, R22 and C26. Good starting values are C26 = 220pF and R21 = 560R, R22 = 4k7. This design used pulse width modulation with logic pulses applied to the CL0_WHITE net (3.3V applied = no output current). You might want to keep this as an emergency stop, or even as a way of checking transient response of things you are testing. R20 and R36 are the current sense resistors (I used 2 because 2 x 1R were much cheaper than 1 x 0.5R). The current is set by the voltage on the CL0_ALL net. If you want a current of 2A max I suggest you set the current sense resistor to 0.22 ohms. Now you will need 0.44 V max. If you use a nice modern op amp like OPA192 with a 10V op amp supply you will be able to drive the MOSFET full on but the low offset voltage of the OPA192 (25uV max at 25C) will only result in a zero error current of 113uA which seems OK. You'll need to pot down the signal from your current control from 0 - 3.3V to 0 - 0.44V. If the modulation pin is to be able to turn the MOSFET off with maximum current demand and 3.3V applied R23/(3.3 - 0.6 - 0.5) = R22/0.5, so R23 = 4.4 * R22. For R22 = 4K7 use 20k for R23. R40 was for current monitoring and went off to an ADC. You can simulate how this will work quite well using (free) TINA from TI. If you can't get the OPA192 almost any 10V rail to rail CMOS op amp would do but most will have much worse offset voltages. MK

jw0752 · Answer

Hi Hendrik,

Thank you for taking the time to give me some guidance. You have zeroed in on all the patches that I had to make to compensate for the non-R to R Op amps. I used R6 to move the ground of U2 relative to U1 so that I could bring the output to zero. I initially used the junction drop of a schottky diode but the temperature sensitivity of the diode made the load setting drift. The Cap C4 was a way to stabalize a more serious oscillation problem. Based on your advice I am going to go back and redo using R to R Op Amps and I will up the supply to the Op Amps. The only reason I used the LT1006 was that I had some and all my R to R Op Amps are SMD and I was too lazy to use them. I originally used 5 volts as this was the voltage required by the electronic ammeter. Ultimately I had to provide an isolated supply for that anyway so there is no need to stay at 5 volts. I have also noted your other suggestions and will incorporate them in the revised circuit. I hope the re do is as much fun as the original build was.

John

jw0752 · Answer

Hi Jon, Thank you for taking the time to simulate the circuit. I had a feeling that my fix was not very elegant. I will find the time in the near future to open the unit back up and start to apply some of the things I have learned from you guys. I left my test points on the board so it will be fairly easy to add and remove trial components to the board. John

jw0752 · Answer

Hi Michael, Jon, Frank, Razvan, and Hendrik, I want you to know that your suggestions are not wasted on me. Since I last posted on this discussion I have ordered in some OPA 192 Op Amps, Some of the TI SO 8 adapter boards and I have gone back to bread boarding and experimenting with your suggestions. I wanted to get a design that used good Op Amp practices and was stable over the desired current and voltage ranges. I began my redesign by changing the reference voltage section to use a TL431 at its lowest setting 2.5 Volts. The application of this voltage to pin 3 of the OPA192 was controlled by a 10K 10T potentiometer. The resistance of R3 was lowered to 47 Ohms. I began my testing with a direct connection between the sense resistor and pin 2 of the OPA but I found that I got oscillations at low input voltages and moderate 500 mA to 1 A currents. While I hadn't seen a resistor in the connection between the sense resistor and pin 2 there was one in Michaels recommended circuit. When I put a 4K7 between the sense resistor and the pin 2 of the OPA192 I saw an immediate improvement in the performance of the circuit. I next moved on to the small capacitor between the OPA output pin 6 and pin 2. I began at 30 pF which also improved performance. This was gradually increased to 200 pF (which was a recommended value). At 200 pF the circuit remained stable over the entire test range. With the excellent suggestions I feel that I have simplified the circuit and feel very good about its stability. Michael if you can tell me what is the reason and side effect of the 4K7 at R2 it would be appreciated. Frank, just a side note. I am used to using Chinese adapter boards and I found the TI boards to be much better quality. However, I had just mounted 16 SO-8 chips onto Chinese boards in the last couple days so I was very used to their orientation and true to my form I didn't look carefully before I orientated the OPA 192 on the TI adapter board. The TI adapter is 180 degrees different from the Chinese boards. Of course I got it on backwards !! Fortunately I was able to scrape off the two pin numbers and redesignate pin 1 with some white paint. Here is my bench test set up for this experiment and a copy of the schematic for the best circuit design so far. Thanks to everyone, hopefully I haven't beat this topic to death yet. John

fmilburn · Answer

Hi John, I have been working through a TI training series on opamps. There is a section on stability that is quite good and the first video gives a very good introduction that I found worth the few minutes it takes to watch it: https://training.ti.com/ti-precision-labs-op-amps-stability-1?cu=14685 Frank

fmilburn · Answer

Hi John, Yes, there is no comparison on the quality of the less expensive Chinese adapters and the TI - ENIG and quality solder mask on the TI adapters makes soldering much easier. I know just the rotated TI adapter you are talking about also. I don't know why they did that and the pin numbers are really hard to read.

michaelkellett · Answer

Hello John, When you put the the power FET on the output of the op amp and take feedback from the "hot" side of R5 you put an RC network and the gate capacity of the MOSFET, as well as the gate voltage to source current dynamics of the MOSFET, inside the feedback loop. OP amps are often stable with unity gain on their own but rarely so with much additional phase error added. The answer is to reduce the gain of the op amp at high frequencies (well one, and often the simplest answer) - on old fashioned devices like LM308, with pins for a compensation capacitor you could just make this rather larger than normal. Most modern devices don't have the extra pins so you need a capacitor from op amp output to -ve input. Without R2 the extra capacitor is trying to drive R5, which in this design is a very low value so the capacitor would be huge, (and even if R5 were 1k it still wouldn't work because the capacitor would be bypassing the MOSFET gate to source.) By adding R2 we isolate the HF feedback from affecting the MOSFET source voltage and allow for C2 to be a reasonable value to introduce a dominant HF roll off and allow the circuit to be stable. (You can also 'explain' this with lots of equations and Nyquist diagrams etc, but I find an intuitive explanation more useful.) Hope that helps. MK

Simple Electronic DC Load Conditional Oscillations

Top Replies