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  • Author Author: Jan Cumps
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Programmable Electronic Load - Power Stage

This blog documents focuses on the power stage of the electronic load that , and are designing.

 

image

In this post we're laying out a PCB for the power stage - as much as possible with surface mount components. The FET is close to the one uses in the original design.

 

The BOM

 

ComponentHeader 2Header 3Header 4
P18 pin header, 2.54mm
P2 abinding post, redhirschmann 931714101hirschmann 931714101 -  SOCKET, 4MM, BLACK, PK5 , MLS
P2 bbinding post, blackhirschmann 931714100hirschmann 931714100 -  SOCKET, 4MM, BLACK, PK5 , MLS
P3 abinding post, blacktenma 2301tenma 2301 - Binding Post, 36 A, 500 V, Nickel Plated Contacts, Panel Mount, Black
P3 bbinding post, redtenma 2302tenma 2302 - Binding Post, 36 A, 500 V, Nickel Plated Contacts, Panel Mount, Red
TH1NTC Thermistor, 10KVishay NTCS0805E3103JLTVishay NTCS0805E3103JLT -  THERMISTOR, 10K, 5%, SMD, NTC
Q1N-Channel MosfetInfineon IRF3205SPBFInfineon IRF3205SPBF -  MOSFET Transistor, N Channel, 110 A, 55 V, 8 mohm, 10 V, 4 V
D1, D2DiodeDIODES SBR2A40P1-7DIODES SBR2A40P1-7 -  Standard Recovery Diode, PowerdiRegistered, 40 V, 2 A, Single, 500 mV, 50 A
R1100R1206 any brand
R20R05Vishay WSHP2818R0500FEBVishay WSHP2818R0500FEB -  SMD Current Sense Resistor, 0.05 ohm, 10 W, 2818 [7146 Metric], ± 1%, WSHP2818 Series
Cooler HeatsinkStartech.com FAN370PRO - Socket 7/370 CPU Cooler Heatsink and Fan

 

 

 

NTC

 

For a detailed description on the temperature protection mechanism, check Programmable Electronic Load - Temperature Protection.

 

The voltage sent to the ADC is very dependent on the NTC. I've selected a Vishay NTCS0805E3103JLTVishay NTCS0805E3103JLT -  THERMISTOR, 10K, 5%, SMD, NTC.

I'll program the key values. The behaviour is non-linear and it's easier to make a lookup table if the firmware has to be able to deal with different components.

This will require access to flash to permanently store tha values, and a SCPI function to alter the table if another component is used.

For the first version I'm going to be selfish and just program for the device that I've ordered.

image

 

PCB

 

Exposed copper

 

For good thermal relief, and to get the NTC as good termally coupled to the FET as possible,

I placed a copper pour (here on the front, I'll do the same on the back and stitch them for thermal transport with vias)

Then i drew a pour on the front mask. The area of pour will expose copper. That means that the NTC has physical contact with the copper that the FET is soldered on.

In the fine-tuning I will place that NTC closer to the FET so that I can put a tad of heat paste in between. Or I could put a tad of paste between the NTC and exposed copper ...

image

 

Attention when placing the binding posts. For the power input, RED is 1 and BLACK is 2.

For the sense input, BLACK is 1 and RED is 2.

This is the result of me labeling pin 7 and 8 of the connectors between the driver board and FET board wrong, on both boards image.

The documentation and KiCAD zips are now updated with corrected schematics.

 

I used these 2 Contextual Electronics videos to refresh how to expose copper layers and place VIA arrays:

 

Here's the top side of the completed design. I've drawn the FET in green to give perspective.

image

In red you see the copper layer, orange is where the solder mask is removed and copper exposed.

Pink are the drill holes. They are 0.9652 mm, in an array of 9 * 8, spaced 2 mm apart.

image

 

On the bottom, the copper pad (green) has the size of my heat sink + some. The removed mask (blue) has the exact size of the sink's bottom profile.

The pink lines are the mounting slots for the heat sink (see below).

image

 

Slots

 

My heat sink has brackets for mounting. I've cut out slots to allow the brackets to through the PCB and fix them on the top side.

 

image

 

I've put some exposed non-connected copper pour around the slots for strength.

The slot is drawn on the Edge.Cuts layer. I hope that the PCB fab interprets that as slots to be milled out ...

image

 

I've attached the KiCAD project, component libs and Gerbers in a single zip. Also the VIA lib that's used here as a separate file (because I share that one across projects).

Attachments:
vias.pretty.zip
eload_offboard_20171227.zip
  • in reply to michaelkellett

      wrote:

     

    image

    I don't mind. It's the nature of electronics prototyping with power components - and doing multiple hardware modifications for learning purposes image. I think it makes hardware electronics more exciting than firmware projects.

    The good news is that the logic part has never died during the prototyping. We took measures to isolate the microcontroller/PC part from the electronics regulation part.

     

    If I were a commercial entity and had the budget, I would use different connectors to connect boards together, and would order 10 PCBs instead of 3 - and some spare components.

    It would not be a high bill 100, maybe 200 €. But that's not what I can spend extra on this device.

  • in reply to michaelkellett

    Yes. It fried in a millisecond when I was doing experiments with the control loop electronics.

    The control board (not the  red board here with this FET on) suffers from many modifications I did during and after this project.

    Board to board connectors and some pads are getting flaky.

     

    I haven't checked the damage on the control board yet.

    But given that gate, drain and source of the power FET are as good as shorted when I measure them, I wouldn't be surprised if the quad-OpAmp gave up too. Possibly also the ADC / DACs / voltage reference.

    That's the next thing I'll check ...

  • in reply to Jan Cumps

    I replaced the mosfet again. It's the 2nd time that I replace the fet. I'm getting better at it image.

     

      imageimage

  • in reply to michaelkellett

      wrote:

     

    Good luck - there's an interesting document from Cree about thermal design of pcbs (focused on LED applications but generally useful).

     

    You can find it by Googling 'XLamp_PCB_Thermal'.

     

    It's good because it gives numbers for via conductivity and even compares solder filled with plain as well as other useful stuff.

     

    I know it's  a bit late now since you've designed your board image

     

    MK

    I'm not very impressed with my own heat dissipation design, . I'm not far off from the document you referred too. Still, my FET runs hot.

    I've got the stitches between front side and back side of the PCB filled with solder, and my fan-cooled heat sink on the backside has a full contact with the PCB's backside.

     

    The heat sink is cold to the touch - lower than room temperature. The FET on the other side runs uncomfortably hot.

  • I've replaced the power MOSFET. It gave up during a test.

    image

    It took some convincing to remove the device because it's sitting on a decent pathc of copper.

    I removed the heatsink from the backside of the pcb, preheated the board to 150 ° and then blasted it off with 440°C hot air.

    I used a desolder device to clean up the solder from the big pad. I couldn't throw enough heat into that pad to use wick.

  • in reply to Robert Peter Oakes

      wrote:

     

    The minus 6.8 gain was because of 5A and a 0.05 ohm sense  and a 2.048 vref

    as per original design.

     

    If the new vref is 4.096 or something this will need re calculating and the

    same goes for changing the sense resistor or current range

     

    Keep the output just under the max of the ADC so it can detect overloads

     

    Peter

    The parameters that are influenced by the reference, sense resistor and opamp gain are fixed in firmware at the moment.
    I'll make them configurable in the calibration/setup api.

    The same situation for the ADC bias and any non-linearity: I haven't implemented decent compensation / correction yet.

    For the DAC/current set part, I haven't even started to investigate the formulas that define the DAC setting for a given current. I'm still using the raw commands to set the DAC between 0 and 65535.
    Now that I have a working device it will be easier.

    I'll also build in the over-power protection.

  • in reply to jc2048

    The minus 6.8 gain was because of 5A and a 0.05 ohm sense  and a 2.048 vref

    as per original design.

     

    If the new vref is 4.096 or something this will need re calculating and the

    same goes for changing the sense resistor or current range

     

    Keep the output just under the max of the ADC so it can detect overloads

     

    Peter

  • in reply to Jan Cumps

    The 50k on U3B shouldn't make any difference now with only 50pA of bias current.

     

    The gain is -6.8 because that's what it's designed to be - simply 680k/100k.

     

    I think there's a case for leaving the 680k to ground. With it, the input is measured with respect to the ground at the sense resistor and the output is with respect to the local ground near the op-amp. Without it, the output is with respect to the sense resistor ground and may differ slightly from the local ground if there are supply currents causing voltage drops along the ground as it passes from board to board.