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  • Author Author: Jan Cumps
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Programmable Electronic Load - Power Stage

This blog documents focuses on the power stage of the electronic load that , and are designing.

 

image

In this post we're laying out a PCB for the power stage - as much as possible with surface mount components. The FET is close to the one uses in the original design.

 

The BOM

 

ComponentHeader 2Header 3Header 4
P18 pin header, 2.54mm
P2 abinding post, redhirschmann 931714101hirschmann 931714101 -  SOCKET, 4MM, BLACK, PK5 , MLS
P2 bbinding post, blackhirschmann 931714100hirschmann 931714100 -  SOCKET, 4MM, BLACK, PK5 , MLS
P3 abinding post, blacktenma 2301tenma 2301 - Binding Post, 36 A, 500 V, Nickel Plated Contacts, Panel Mount, Black
P3 bbinding post, redtenma 2302tenma 2302 - Binding Post, 36 A, 500 V, Nickel Plated Contacts, Panel Mount, Red
TH1NTC Thermistor, 10KVishay NTCS0805E3103JLTVishay NTCS0805E3103JLT -  THERMISTOR, 10K, 5%, SMD, NTC
Q1N-Channel MosfetInfineon IRF3205SPBFInfineon IRF3205SPBF -  MOSFET Transistor, N Channel, 110 A, 55 V, 8 mohm, 10 V, 4 V
D1, D2DiodeDIODES SBR2A40P1-7DIODES SBR2A40P1-7 -  Standard Recovery Diode, PowerdiRegistered, 40 V, 2 A, Single, 500 mV, 50 A
R1100R1206 any brand
R20R05Vishay WSHP2818R0500FEBVishay WSHP2818R0500FEB -  SMD Current Sense Resistor, 0.05 ohm, 10 W, 2818 [7146 Metric], ± 1%, WSHP2818 Series
Cooler HeatsinkStartech.com FAN370PRO - Socket 7/370 CPU Cooler Heatsink and Fan

 

 

 

NTC

 

For a detailed description on the temperature protection mechanism, check Programmable Electronic Load - Temperature Protection.

 

The voltage sent to the ADC is very dependent on the NTC. I've selected a Vishay NTCS0805E3103JLTVishay NTCS0805E3103JLT -  THERMISTOR, 10K, 5%, SMD, NTC.

I'll program the key values. The behaviour is non-linear and it's easier to make a lookup table if the firmware has to be able to deal with different components.

This will require access to flash to permanently store tha values, and a SCPI function to alter the table if another component is used.

For the first version I'm going to be selfish and just program for the device that I've ordered.

image

 

PCB

 

Exposed copper

 

For good thermal relief, and to get the NTC as good termally coupled to the FET as possible,

I placed a copper pour (here on the front, I'll do the same on the back and stitch them for thermal transport with vias)

Then i drew a pour on the front mask. The area of pour will expose copper. That means that the NTC has physical contact with the copper that the FET is soldered on.

In the fine-tuning I will place that NTC closer to the FET so that I can put a tad of heat paste in between. Or I could put a tad of paste between the NTC and exposed copper ...

image

 

Attention when placing the binding posts. For the power input, RED is 1 and BLACK is 2.

For the sense input, BLACK is 1 and RED is 2.

This is the result of me labeling pin 7 and 8 of the connectors between the driver board and FET board wrong, on both boards image.

The documentation and KiCAD zips are now updated with corrected schematics.

 

I used these 2 Contextual Electronics videos to refresh how to expose copper layers and place VIA arrays:

 

Here's the top side of the completed design. I've drawn the FET in green to give perspective.

image

In red you see the copper layer, orange is where the solder mask is removed and copper exposed.

Pink are the drill holes. They are 0.9652 mm, in an array of 9 * 8, spaced 2 mm apart.

image

 

On the bottom, the copper pad (green) has the size of my heat sink + some. The removed mask (blue) has the exact size of the sink's bottom profile.

The pink lines are the mounting slots for the heat sink (see below).

image

 

Slots

 

My heat sink has brackets for mounting. I've cut out slots to allow the brackets to through the PCB and fix them on the top side.

 

image

 

I've put some exposed non-connected copper pour around the slots for strength.

The slot is drawn on the Edge.Cuts layer. I hope that the PCB fab interprets that as slots to be milled out ...

image

 

I've attached the KiCAD project, component libs and Gerbers in a single zip. Also the VIA lib that's used here as a separate file (because I share that one across projects).

Attachments:
vias.pretty.zip
eload_offboard_20171227.zip
  • in reply to jc2048

      wrote:

     

     

    Is that back to the original circuit or the later one with the extra resistors to balance the bias currents?

    It has got the 680 K resistor in the current sense (R32). It turns the gain from -7.8 to -6.8. I haven't tested the circuit without it yet.

     

    I've not soldered the 50 K between U3B+ and ground.

    I have bent that pin 5 of the opamp up in the air so that it can be bodged at will. Currently it's connected it directly to ground with a wire.

    I can easily solder the 50 K in and see the effect in measurement ...

  • in reply to Jan Cumps

    Good progress. That's much better.

     

    Is that back to the original circuit or the later one with the extra resistors to balance the bias currents?

  • in reply to Jan Cumps

    Results are rather good:

    Line 1 is sampled current

    line 2 input at the sense connectors.

    image

     

    Measured values

    1.334 A

    14.89 V

  • in reply to Jan Cumps

    Fixed. Bad solder joint. The board starts to suffer from too many interventions.

    The lowest point is 3 mA. That's a bunch better than the 2xx mA I had before.

  • in reply to Jan Cumps

    I've placed the other opamp, a LINEAR TECHNOLOGY LT1058, and the output is very unstable.

    With the original opamp the output current was always fixed when I set the DAC to a value. With this one, it jumps all over the place, looks like oscillating ...

  • in reply to Jan Cumps

    Back in business. DAC, ADC, ref and port expander all work. Time to replace the opamp with the low bias one.

    image

  • in reply to Robert Peter Oakes

      wrote:

     

    Ouch.  That sucks. I am curious how it took out everything.  Can't wait for pictures

    I've got the new ADC/DAC board fully functional. I recovered the missing chips from previous pcbs that I had built earlier on for this exercise.

    I can't afford a new incident with that board though, because I've now used the last pcb.

    For the driver board I only have one pcb, so I'll have to be careful when reworking that one - and I haven't ordered a port expander replacement yet.

  • in reply to Robert Peter Oakes

      wrote:

     

    So a little tweaking with the table should fix that I think... nice work

    At the moment the firmware doesn't hold a table for the NTC.

     

    I was doing raw measurements with the ADC,
    then deriving the NTC value through voltage divider formula,
    and looking up the corresponding temperature in the datasheet.

     

    At this moment, the firmware and calibration api support a single point that you can set, where the device should shut off.

    You look up the resistor value of the NTC at the temperature you want to set as maximum, then call the calibration SCPI commands to save that.

    When the firmware detects that the resistance goes below that set value, the input is shut off.

     

    You can change the setting at run-time temporary (for as long as the device is powered on) or store a new value later if desired.

     

    I've not implemented a means to measure and display current temperature across the range because not convinced yet on how to do it in a way that doesn't require code recompilation and doesn't make initial calibration and setup tedious.

    I'm parking it for now as it doesn't impact the devices operation. I've added it to the todo list on the main post.

  • in reply to Jan Cumps

    ... of all the measurement-destroy incidents in my lifetime, this is the least exciting (no fire, no noise) mishap.

    But it took down everything made of silicon (note to self:check the power FET) up to (and including)  the isolation level (thank you for adding that layer).

  • in reply to Jan Cumps

    The only IC I reused was the isolator IC U1 (because TI doesn't hold stock at this moment and I could not back-order it from their store ).

    The reused one seems to have a bad clock on the isolated side - as in: no clock at all while the micro controller side shows a beautiful clock signal (more checking needed).

    Ground to clock resistance on the isolated side is 12 R - regardless of polarity. Because the isolation IC is the only reused one, I'm blaming that. I'll remove it (not too bad, it's got a doable SOIC footprint).

     

    I ordered a few new ones from another source - had to add a load of lead-free solder to dodge the transport costs.

     

    edit: some luck: I used leaded paste for the ICs, lead-free hand solder for the passives. Because the ICs are separated by the passives, I can remove a single one with hot air without blowing away the passives. The higher melting temperature of the lead-free solder plays to my advantage this time.