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At The Core Design Challenge
Blog AtTheCore: Blog #4 - Adding shared PWM, Testing with Scope and all about Dual-Core
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  • Author Author: navadeepganeshu
  • Date Created: 3 May 2023 3:18 PM Date Created
  • Views 870 views
  • Likes 6 likes
  • Comments 2 comments
  • infineon
  • PSoC 62S4 pioneer kit
  • modustoolbox
  • dual-core
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AtTheCore: Blog #4 - Adding shared PWM, Testing with Scope and all about Dual-Core

navadeepganeshu
navadeepganeshu
3 May 2023
AtTheCore: Blog #4 - Adding shared PWM, Testing with Scope and all about Dual-Core

Table of Contents

  • Introduction
  • Adding multiple shared pins for PWM
  • Testing Clips - PWM sweep using Capsense
  • IFX007T Motor Control Shield 
  • PSoC Dual-Core concepts
  • Gearing Further
  • References
  • Also read

Introduction

In this blog, we'll have a closer look at multi PWM control using capsense slider and how a single peripheral signal can be shared between PSoC pins. Next it is all about linking bits and pieces together and running a dual-core application. This PWM pin will be an input to the IFX007T motor driver shield for controlling two DC motors in half-bridge configuration. I also got to learn about dual core concepts and how PSoC is configured and handles these - to which we'll quickly jump into at the end of this blog.

Adding multiple shared pins for PWM

In the last blog, I configured the LED for PWM referring to the example project and then scaled it to have two separate PWM signals driving LEDs onboard. Now the motor control is to be established using the IFX007 motor controller. So for this matter, this particular PWM signal controlling the LED is split up and the signal is also given to the motor driver control pin. The device configurator in the ModusToolbox helps us to do this in an intuitive way. As shown in the image attached below, going to the PWM selection channel whichever we want to setup, we can add multiple output pins inking to this particular PWM channel. The same goes with PWM1 and PW2 with 2 pins each shared from a respective TCPWM peripheral controller. 

image

The configurations for shared pin being done, the pins P0[5] and P5[7] are probed to see the PWM signal which would eventually be connected to the motor driver INU and INV pins. RedPitaya is a small nice web-based GUI tool having multi-function. This is used as an oscilloscope here for the testing.

image

Testing Clips - PWM sweep using Capsense

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IFX007T Motor Control Shield 

This shield comes with 3 half-bridge drivers and is suitable for DC and BLDC motors. Here, I am using it for driving two motors using U and V half-bridge channels (here is my RoadTest review in this kit published way back with kind sponsorship from Infineon and E14 Navadeep's RoadTest Review on Infineon BLDC Shield + XMC 4700 Relax Kit + Motor) 

Having a look at the application information about how to use a DC motor, here is a schematic that I found real quick and two motors are connected individually the same way(no luxury of reverse protections in my circuit btw) and INU, INV control pins and INHU, INHV inhibit pins come from PSoC. The inhibit pins are a real cool feature available in this chip which can be used to perform emergency stops or to disable motors inside certain function loops in the code. 

  image

PSoC Dual-Core concepts

Dual-core implementation being the main goal of this challenge, I decided to dig a bit more into these and hit across multiple documentation and application notes. Here are some learnings:

imageimage

1. IPC message Passing: The IPC channel is used to lock access to the data registers. The IPC channel is acquired by the sender and used to populate the message. The receiver reads the message and then releases the channel. Thus, between the sender putting data into the channel and the receiver reading it, the channel is locked for all other task access. 

2. CPUs: CM4 is the main CPU. It is designed for a short interrupt response time, high code density, and high throughput. The CM0+ CPU is secondary; it is used in PSoC6 MCU to implement system calls and device-level security, safety, and protection features.

3. Booting and Startup Sequence: This process is extremely carefully and precisely handled by the device. After reset, the boot code starts execution from ROM on the CM0+ and CM4 is held in a reset state. CM0+ first executes the Infineon system and security code, including SROM code, FlashBoot, and Secure Image.

Gearing Further

In the next blog, we'll see the exciting part of linking all sections and running the application of motor control with slider and ambient light sensing all running on separate cores and how the data is shared through IPC pipe. Whoops! It's working and awaited to be tested fully...

Thanks for reading through this and do share your feedback/queries/idea on these. I might have gotten saturated working on this and do let me know in the comments if I am missing any understanding hooks in the project build flow. Happy to discuss around. Thank you Slight smile

References

PSoCTm 6 MCU dual-core system design (infineon.com)
PSoC® 6 MCU Dual-Core Basics (infineon.com)
PSoC 6 Peripheral Driver Library: PDL API Reference (infineon.github.io)

https://www.infineon.com/dgdl/Infineon-IFX007T-DS-v01_00-EN.pdf

PSoC 6 MCU: CY8C61x4, CY8C62x4 Architecture Technical Reference Manual (TRM) PSoC 61, PSoC 62 MCU (infineon.com) long TRM hurts often!

Also read

 AtTheCore: Blog #1 - Intro and what's up with the kit! 

 AtTheCore: Blog #2 - Interfacing LED Bar with ALS 

 AtTheCore: Blog #3 - PWM and Capsense on Cortex M0+ 

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  • navadeepganeshu
    navadeepganeshu over 2 years ago in reply to DAB

    Thanks DAB. I am now trying to integrate them all try curtain control application. The following blog coming up in a while,...

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  • DAB
    DAB over 2 years ago

    Nice update.

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