My initial idea for the last training blog on the "Path to Programmable 3" challenge was to dedicate it to write about my experiences tinkering with the WIFI and Bluetooth communication of the MiniZed dev board. The road soon went wrong.

There are only drivers for the Murata module for Linux and the documentation is not accessible or I can't find it. So I had to reset the schedule one more time and start the Petalinux training course.

During all the experiments in this blog it is recommended to use the second USB power connector to power the USB Host interface of the Avnet MiniZed development board as in the image.

Murata LBEE5KL1DX wireless module

I started by looking at the built-in Murata LBEE5KL1DX wireless module on the Avnet MiniZed development board. The Murata LBEE5KL1DX is a module that supports Wi-Fi 802.11b/g/n and Bluetooth 4.1/EDR.

References for the LBEE5KL1DX-883

• https://www.murata.com/en-us/products/connectivitymodule/wi-fi-bluetooth/overview/lineup/type1dx
• https://www.murata.com/products/productdata/8813651165214/type1dx.pdf
• CYW4343W Single-Chip 802.11 b/g/n MAC/Baseband/Radio with Bluetooth 4.1 (infineon.com)

MiniZed Wireless - Sensors Schematic

Extract of the schematic of the Avnet Minized development board where we can locate the Murata wireless communications module.

Wireless module software support

As for software support, that's where my problems began. I was hoping that there would be a driver or enough information to communicate in bare metal with the module, but it is not. Unfortunately standalone Zynq projects are not supported, only Linux using either the bcmdhd or brcmfmac Broadcom drivers are supported.

I didn't want to get into Petalinux training yet as I knew it would be very tedious and I would have to switch from windows to Linux learning environment and from a powerful native windows machine to a snail-like virtual machine.

Zynq to wireless module interface

The diagram shows how the Zynq PS peripherals are connected to the 1DX module.

• All wireless I/O are connected via EMIO
• All 4 UART signals (Tx, Rx, CTS and RTS) are used for the Bluetooth/BLE interface
• All 6 SDIO signals are used for the Wi-Fi interface
• 4 of the 1DX GPIO signals are connected for handshaking
  • BT_REG_ON
  • BT_HOST_WAKE
  • WL_REG_ON
  • WL_HOST_WAKE
• The PCM interface is not connected. This is typically used for driving a Bluetooth speaker directly

Wireless Manager VHDL Adapter

In order to easily incorporate wireless communications, Avnet provides us with a VHDL module that routes and acts as a buffer for the SDIO communications of the WIFI module and the UART of the Bluetooth module.

We can add, for example, to a block design or instantiate it directly from another module, it does not have any type of AXI control.

And a complete design created from scratch in Vivado version 2022.2 and 2022.1. With Vivado 2022.2 version Vivado generates an exception when generating the bitstream, but it works fine with Vivado 2022.1

There is no software support for bare metal applications (Zynq standalone), so we will go the way of Petalinux.

Going to Petalinux

I have followed the first two parts of the training, Software and Hardware, using AMD Vivado ML version 2022.2. It has been a very good experience and I have hardly had any problems that have been easily solved.

Since version 2022.2 has been very friendly to me, I thought about installing the same version of Petalinux in a virtual machine with Ubuntu. The Petalinux installation went well. My problems started with not finding Avnet support for Minized with this version of AMD Vivado ML tools. So after dozens of lost hours, I returned to the path marked out by the course and reinstalled version 2021.1 of Vivado.

PetaLinux Project Structure

A built Linux system is composed of the following components:

• Device tree
• First stage boot loader (optional)
• U-Boot
• Linux kernel
• The root file system is composed of the following components:
  • Prebuilt packages
  • Linux user applications (optional)
  • User modules (optional)

A PetaLinux project directory contains configuration files of the project, the Linux subsystem, and the components of the subsystem. The petalinux-build command builds the project with those configuration files. You can run petalinux-config to modify them.

References:

• PetaLinux Tools for Embedded Linux Development (xilinx.com)
• PetaLinux Tools Documentation: Reference Guide (xilinx.com)

Petalinux commands

There are eight independent commands that make up the PetaLinux design flow. They are:

• petalinux-create: 
  • petalinux-create -t project workflow, the tool creates a new PetaLinux project directory structure.
  • petalinux-create -t COMPONENT workflow, the tool creates a component within the specified project (apps, kernel modules)
• petalinux-config: allows you to customize the specified project or component with a menuconfig interface
• petalinux-build: builds either the entire embedded Linux system or a specified component of the Linux system
• petalinux-boot:  boots MicroBlaze CPU, Zynq devices, Versal ACAP, and Zynq UltraScale+ MPSoC with PetaLinux images through JTAG/QEMU software emulator.
• petalinux-package:  packages a PetaLinux project into a format suitable for deployment.
• petalinux-util:  provides various support services to the other PetaLinux workflows: gdb, dfu-util, xsdb-connect, jtag-logbuf, find-xsa-bitstream
• petalinux-upgrade: To upgrade the workspace
• petalinux-devtool: uses the Yocto devtool to enable you to build, test, and package software.

Creating and Installing Petalinux images

We need to first install a minimum PetaLinux on the Minized using  the QSPI Flash that loads from eMMC Flash memory. Then use PetaLinux to program additional larger PetaLinux images.

First step: configure and boot a minimal PetaLinux image.

We will setup and configure a minimal PetaLinux system using the PetaLinux tools. The minimal image will be loaded into the 16MB qspi memory which will be loaded onto the 512MB DDR3L.

It takes a long time to complete a new PetaLinux project. In my case it took about 8 hours. You also can work with the prebuilt images.

First clone the Avnet git repositories. There three repositories and it is recommended no to change the names of the directories.

• git clone https://github.com/avnet/bdf.git  / master branch
• git clone https://github.com/avnet/hdl.git / 2021.1 branch
• git clone https://github.com/avnet/petalinux.git /2021.1 branch

It is important to check out the correct branch.

Then to create the BSP we have to execute the make_minized_sbc_base.sh script under petalinux/scripts.

PetaLinux environment set to '/tools/petalinux-v2021.1-final'
INFO: Checking free disk space
INFO: Checking installed tools
INFO: Checking installed development libraries
INFO: Checking network and other services
ealbertos@ealbertos-VirtualBox:~$ cd ~
ealbertos@ealbertos-VirtualBox:~$ mkdir -p git/avnet
ealbertos@ealbertos-VirtualBox:~$ cd git/avnet
ealbertos@ealbertos-VirtualBox:~/git/avnet$ git clone https://github.com/avnet/bdf.git
Cloning into 'bdf'...
remote: Enumerating objects: 654, done.
remote: Counting objects: 100% (58/58), done.
remote: Compressing objects: 100% (30/30), done.
remote: Total 654 (delta 35), reused 33 (delta 26), pack-reused 596
Receiving objects: 100% (654/654), 34.90 MiB | 5.60 MiB/s, done.
Resolving deltas: 100% (323/323), done.
ealbertos@ealbertos-VirtualBox:~/git/avnet$ git clone https://github.com/avnet/hdl.git
Cloning into 'hdl'...
remote: Enumerating objects: 6154, done.
remote: Counting objects: 100% (1817/1817), done.
remote: Compressing objects: 100% (551/551), done.
remote: Total 6154 (delta 1228), reused 1710 (delta 1168), pack-reused 4337
Receiving objects: 100% (6154/6154), 15.13 MiB | 6.90 MiB/s, done.
Resolving deltas: 100% (3792/3792), done.
Checking out files: 100% (1874/1874), done.
ealbertos@ealbertos-VirtualBox:~/git/avnet$ git clone https://github.com/avnet/petalinux.git
Cloning into 'petalinux'...
remote: Enumerating objects: 3880, done.
remote: Counting objects: 100% (809/809), done.
remote: Compressing objects: 100% (165/165), done.
remote: Total 3880 (delta 677), reused 700 (delta 622), pack-reused 3071
Receiving objects: 100% (3880/3880), 6.24 MiB | 7.69 MiB/s, done.
Resolving deltas: 100% (2282/2282), done.
ealbertos@ealbertos-VirtualBox:~/git/avnet$ cd bdf
ealbertos@ealbertos-VirtualBox:~/git/avnet/bdf$ git checkout master
Already on 'master'
Your branch is up to date with 'origin/master'.
ealbertos@ealbertos-VirtualBox:~/git/avnet/bdf$ cd ../hdl
ealbertos@ealbertos-VirtualBox:~/git/avnet/hdl$ git checkout 2021.1
Branch '2021.1' set up to track remote branch '2021.1' from 'origin'.
Switched to a new branch '2021.1'
ealbertos@ealbertos-VirtualBox:~/git/avnet/hdl$ cd ../petalinux/
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux$ git checkout 2021.1
Branch '2021.1' set up to track remote branch '2021.1' from 'origin'.
Switched to a new branch '2021.1'
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux$ cd ~/git/avnet/petalinux/scripts/
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/scripts$ source /tools/Xilinx/Vivado/2021.1/settings64.sh
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/scripts$ ./make_minized_sbc_base.sh

Verifying repositories ...


Checking Environment (Xilinx tools sourced) ...


Checking 'minized_sbc_base_2021_1' Vivado Project ...


No built Vivado HW project minized_sbc_base_2021_1 found.
Will build the hardware platform now.


****** Vivado v2021.1 (64-bit)
  **** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
  **** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source make_minized_sbc_base.tcl -notrace

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-                                                     -*
*-        Welcome to the Avnet Project Builder         -*
*-                                                     -*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Selected 
 BDF path /home/ealbertos/git/avnet/bdf
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


Creating projects Folder

+------------------+------------------------------------+
| Setting          |     Configuration                  |
+------------------+------------------------------------+
| Board            |     minized_sbc                    |
+------------------+------------------------------------+
| Project          |     base                           |
+------------------+------------------------------------+
| SDK              |     no                             |
+------------------+------------------------------------+
| No Close Project |     yes                            |
+------------------+------------------------------------+
| Device           |     zynq                           |
+------------------+------------------------------------+



*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Vivado version 2021.1 acceptable, 
continuing...
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*




*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Selected Board and Project as:
 minized_sbc and base
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*




*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Not Requesting Tag
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


 Setting Up Project minized_sbc_base...

***** Creating Vivado project...
create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2377.695 ; gain = 2.016 ; free physical = 3789 ; free virtual = 8166

***** Setting synthesis language for project to VHDL...

***** Importing constraints file(s)...

***** Assigning Vivado project board_part property to minized...

***** Generating IP...

***** Updating Vivado to include IP folder
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ealbertos/git/avnet/hdl/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2021.1/data/ip'.

***** Creating block design...
Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
create_bd_design: Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:06 . Memory (MB): peak = 2446.016 ; gain = 25.062 ; free physical = 3713 ; free virtual = 8136
***** Adding RTL source Files to design...

***** Adding custom RTL IP blocks to block design...
Making wireless_mgr instance wireless_mgr_0 ...
INFO: [IP_Flow 19-5107] Inferred bus interface 'SDIO_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'WL_SDIO_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-5661] Bus Interface 'SDIO_CLK' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-5661] Bus Interface 'WL_SDIO_CLK' does not have any bus interfaces associated with it.
CRITICAL WARNING: [IP_Flow 19-4751] Bus Interface 'WL_SDIO_CLK': FREQ_HZ bus parameter is missing for output clock interface.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ealbertos/git/avnet/hdl/ip'.
Making led_mgr instance led_mgr_0 ...
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ealbertos/git/avnet/hdl/ip'.
Making microphone_mgr instance microphone_mgr_0 ...
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_in' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_in' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn_in' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn_in' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AUDIO_CLK' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AUDIO_CLK' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-4728] Bus Interface 'clk_in': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn_in'.
INFO: [IP_Flow 19-4728] Bus Interface 'clk_in': Added interface parameter 'FREQ_HZ' with value '160000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'AUDIO_CLK': Added interface parameter 'FREQ_HZ' with value '2500000'.
INFO: [IP_Flow 19-7067] Note that bus interface 'clk_in' has a fixed FREQ_HZ of '160000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
WARNING: [IP_Flow 19-5661] Bus Interface 'clk_in' does not have any bus interfaces associated with it.
INFO: [IP_Flow 19-7067] Note that bus interface 'AUDIO_CLK' has a fixed FREQ_HZ of '2500000'. This value will be respected whenever this IP is instantiated in IP Integrator.
WARNING: [IP_Flow 19-5661] Bus Interface 'AUDIO_CLK' does not have any bus interfaces associated with it.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ealbertos/git/avnet/hdl/ip'.

***** Adding processing system presets from board definition...
Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 

***** Adding defined IP blocks to block design...
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Device 21-403] Loading part xc7z007sclg225-1
create_bd_cell: Time (s): cpu = 00:00:03 ; elapsed = 00:00:19 . Memory (MB): peak = 2454.023 ; gain = 0.000 ; free physical = 3289 ; free virtual = 7773
Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKFBOUT_MULT_F' from '10.000' to '20.000' has been ignored for IP 'clk_wiz_0'
Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/xin> is being overridden by the user with net <ps7_FCLK_CLK1>. This pin will not be connected as a part of interface connection <UART>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_0/gpio_io_o> is being overridden by the user with net <axi_gpio_0_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_0/gpio2_io_o> is being overridden by the user with net <axi_gpio_0_gpio2_io_o>. This pin will not be connected as a part of interface connection <GPIO2>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_2/gpio_io_t> is being overridden by the user with net <axi_gpio_2_gpio_io_t>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_2/gpio_io_o> is being overridden by the user with net <axi_gpio_2_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </axi_gpio_2/gpio_io_i> is being overridden by the user with net <led_mgr_0_GPIO_to_Zynq>. This pin will not be connected as a part of interface connection <GPIO>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO1_CDN> is being overridden by the user with net <xlconstant_1_dout>. This pin will not be connected as a part of interface connection <SDIO_1>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO1_WP> is being overridden by the user with net <xlconstant_1_dout>. This pin will not be connected as a part of interface connection <SDIO_1>.
WARNING: [BD 41-1306] The connection to interface pin </axi_intc_0/irq> is being overridden by the user with net <axi_intc_0_irq>. This pin will not be connected as a part of interface connection <interrupt>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CLK> is being overridden by the user with net <ps7_SDIO0_CLK>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CLK_FB> is being overridden by the user with net <wireless_mgr_0_SDIO_CLK_FB>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CMD_O> is being overridden by the user with net <ps7_SDIO0_CMD_O>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CMD_I> is being overridden by the user with net <wireless_mgr_0_SDIO_CMD_to_Zynq>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CMD_T> is being overridden by the user with net <ps7_SDIO0_CMD_T>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_DATA_O> is being overridden by the user with net <ps7_SDIO0_DATA_O>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_DATA_I> is being overridden by the user with net <wireless_mgr_0_SDIO_DATA_to_Zynq>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_DATA_T> is being overridden by the user with net <ps7_SDIO0_DATA_T>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_WP> is being overridden by the user with net <wireless_mgr_0_SDIO_WP>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/SDIO0_CDN> is being overridden by the user with net <wireless_mgr_0_SDIO_CDN>. This pin will not be connected as a part of interface connection <SDIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/GPIO_O> is being overridden by the user with net <ps7_GPIO_O>. This pin will not be connected as a part of interface connection <GPIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/GPIO_I> is being overridden by the user with net <wireless_mgr_0_GPIO_to_Zynq>. This pin will not be connected as a part of interface connection <GPIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </ps7/GPIO_T> is being overridden by the user with net <ps7_GPIO_T>. This pin will not be connected as a part of interface connection <GPIO_0>.
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/sout> is being overridden by the user with net <bluetooth_uart_sout>. This pin will not be connected as a part of interface connection <UART>.
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/sin> is being overridden by the user with net <wireless_mgr_0_ZYNQ_UART_RX>. This pin will not be connected as a part of interface connection <UART>.
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/rtsn> is being overridden by the user with net <bluetooth_uart_rtsn>. This pin will not be connected as a part of interface connection <UART>.
WARNING: [BD 41-1306] The connection to interface pin </bluetooth_uart/ctsn> is being overridden by the user with net <wireless_mgr_0_ZYNQ_UART_CTS>. This pin will not be connected as a part of interface connection <UART>.
Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 

***** Assigning peripheral addresses...
Slave segment '/axi_gpio_0/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4120_0000 [ 64K ]>.
Slave segment '/axi_gpio_1/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4121_0000 [ 64K ]>.
Slave segment '/axi_gpio_2/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4122_0000 [ 64K ]>.
Slave segment '/axi_iic_0/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4160_0000 [ 64K ]>.
Slave segment '/axi_intc_0/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x4180_0000 [ 64K ]>.
Slave segment '/bluetooth_uart/S_AXI/Reg' is being assigned into address space '/ps7/Data' at <0x43C0_0000 [ 64K ]>.
Slave segment '/xadc_wiz_0/s_axi_lite/Reg' is being assigned into address space '/ps7/Data' at <0x43C1_0000 [ 64K ]>.

***** Validating the block design...
Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
CRITICAL WARNING: [BD 41-1348] Reset pin /microphone_mgr_0/resetn_in (associated clock /microphone_mgr_0/clk_in) is connected to asynchronous reset source /ps7/FCLK_RESET2_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ps7/FCLK_CLK2.
WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc_0: Interrupt output connection Bus is selected, but the interrupt bus interface is not connected to a matching interface. Please consider selecting Single instead.
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/axi_intc_0/intr


***** Validating IP licenses...
License Validation = Successful

***** Creating top level HDL wrapper for design and adding to project...
INFO: [BD 41-1662] The design 'minized_sbc_base.bd' is already validated. Therefore parameter propagation will not be re-run.
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/axi_intc_0/intr

Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_from_Zynq'(4) to pin '/ps7/GPIO_O'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/ps7/GPIO_I'(16) to pin '/wireless_mgr_0/GPIO_to_Zynq'(4) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_dir'(4) to pin '/ps7/GPIO_T'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/synth/minized_sbc_base.vhd
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_from_Zynq'(4) to pin '/ps7/GPIO_O'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/ps7/GPIO_I'(16) to pin '/wireless_mgr_0/GPIO_to_Zynq'(4) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_dir'(4) to pin '/ps7/GPIO_T'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/sim/minized_sbc_base.vhd
VHDL Output written to : /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/hdl/minized_sbc_base_wrapper.vhd
INFO: [Project 1-1716] Could not find the wrapper file /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/hdl/minized_sbc_base_wrapper.vhd, checking in project .gen location instead.
INFO: [Vivado 12-12390] Found file /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/hdl/minized_sbc_base_wrapper.vhd, adding it to Project

***** Adding Vitis directves to design...
update_compile_order: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2454.039 ; gain = 0.016 ; free physical = 3206 ; free virtual = 7716
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'

***** Building binary...
update_compile_order: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2454.039 ; gain = 0.000 ; free physical = 3206 ; free virtual = 7716
update_compile_order: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2454.039 ; gain = 0.000 ; free physical = 3205 ; free virtual = 7716
Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
CRITICAL WARNING: [BD 41-1348] Reset pin /microphone_mgr_0/resetn_in (associated clock /microphone_mgr_0/clk_in) is connected to asynchronous reset source /ps7/FCLK_RESET2_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ps7/FCLK_CLK2.
WARNING: [xilinx.com:ip:axi_intc:4.1-13] /axi_intc_0: Interrupt output connection Bus is selected, but the interrupt bus interface is not connected to a matching interface. Please consider selecting Single instead.
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/axi_intc_0/intr

Wrote  : </home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd> 
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_from_Zynq'(4) to pin '/ps7/GPIO_O'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/ps7/GPIO_I'(16) to pin '/wireless_mgr_0/GPIO_to_Zynq'(4) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_dir'(4) to pin '/ps7/GPIO_T'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/synth/minized_sbc_base.vhd
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_from_Zynq'(4) to pin '/ps7/GPIO_O'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/ps7/GPIO_I'(16) to pin '/wireless_mgr_0/GPIO_to_Zynq'(4) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/wireless_mgr_0/GPIO_dir'(4) to pin '/ps7/GPIO_T'(16) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
VHDL Output written to : /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/sim/minized_sbc_base.vhd
VHDL Output written to : /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/hdl/minized_sbc_base_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block wireless_mgr_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block led_mgr_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block microphone_mgr_0 .
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block bluetooth_uart .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconstant_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_intc_0 .
false
INFO: [IP_Flow 19-3422] Upgraded pdm_filt_fir_compiler_v7_2_i0 (FIR Compiler 7.2) from revision 8 to revision 16
false
INFO: [IP_Flow 19-3422] Upgraded pdm_filt_fir_compiler_v7_2_i1 (FIR Compiler 7.2) from revision 8 to revision 16
INFO: [BD 41-1029] Generation completed for the IP Integrator block pdm_filt_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_100MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_142MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_166MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_200MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_41MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_50MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_auto_pc_0/minized_sbc_base_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_axi_periph/s00_couplers/auto_pc .
Exporting to file /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/hw_handoff/minized_sbc_base.hwh
Generated Block Design Tcl file /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/hw_handoff/minized_sbc_base_bd.tcl
Generated Hardware Definition File /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/synth/minized_sbc_base.hwdef
[Fri Jul 14 18:19:35 2023] Launched minized_sbc_base_xbar_0_synth_1, minized_sbc_base_ps7_0_synth_1, minized_sbc_base_microphone_mgr_0_0_synth_1, minized_sbc_base_led_mgr_0_0_synth_1, minized_sbc_base_wireless_mgr_0_0_synth_1, minized_sbc_base_xadc_wiz_0_0_synth_1, minized_sbc_base_pdm_filt_0_0_synth_1, minized_sbc_base_axi_gpio_0_0_synth_1, minized_sbc_base_axi_gpio_1_0_synth_1, minized_sbc_base_axi_gpio_2_0_synth_1, minized_sbc_base_axi_iic_0_0_synth_1, minized_sbc_base_axi_uart16550_0_0_synth_1, minized_sbc_base_axi_intc_0_0_synth_1, minized_sbc_base_auto_pc_0_synth_1, minized_sbc_base_proc_sys_reset_100MHz_0_synth_1, minized_sbc_base_proc_sys_reset_142MHz_0_synth_1, minized_sbc_base_proc_sys_reset_166MHz_0_synth_1, minized_sbc_base_proc_sys_reset_200MHz_0_synth_1, minized_sbc_base_proc_sys_reset_41MHz_0_synth_1, minized_sbc_base_proc_sys_reset_50MHz_0_synth_1, minized_sbc_base_clk_wiz_0_0_synth_1, synth_1...
Run output will be captured here:
minized_sbc_base_xbar_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_xbar_0_synth_1/runme.log
minized_sbc_base_ps7_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_ps7_0_synth_1/runme.log
minized_sbc_base_microphone_mgr_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_microphone_mgr_0_0_synth_1/runme.log
minized_sbc_base_led_mgr_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_led_mgr_0_0_synth_1/runme.log
minized_sbc_base_wireless_mgr_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_wireless_mgr_0_0_synth_1/runme.log
minized_sbc_base_xadc_wiz_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_xadc_wiz_0_0_synth_1/runme.log
minized_sbc_base_pdm_filt_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_pdm_filt_0_0_synth_1/runme.log
minized_sbc_base_axi_gpio_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_axi_gpio_0_0_synth_1/runme.log
minized_sbc_base_axi_gpio_1_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_axi_gpio_1_0_synth_1/runme.log
minized_sbc_base_axi_gpio_2_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_axi_gpio_2_0_synth_1/runme.log
minized_sbc_base_axi_iic_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_axi_iic_0_0_synth_1/runme.log
minized_sbc_base_axi_uart16550_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_axi_uart16550_0_0_synth_1/runme.log
minized_sbc_base_axi_intc_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_axi_intc_0_0_synth_1/runme.log
minized_sbc_base_auto_pc_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_auto_pc_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_100MHz_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_100MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_142MHz_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_142MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_166MHz_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_166MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_200MHz_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_200MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_41MHz_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_41MHz_0_synth_1/runme.log
minized_sbc_base_proc_sys_reset_50MHz_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_proc_sys_reset_50MHz_0_synth_1/runme.log
minized_sbc_base_clk_wiz_0_0_synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/minized_sbc_base_clk_wiz_0_0_synth_1/runme.log
synth_1: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/synth_1/runme.log
[Fri Jul 14 18:19:35 2023] Launched impl_1...
Run output will be captured here: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:52 ; elapsed = 00:01:00 . Memory (MB): peak = 2637.051 ; gain = 183.012 ; free physical = 3009 ; free virtual = 7617

***** Wait for bitstream to be written...
[Fri Jul 14 18:19:35 2023] Waiting for impl_1 to finish...

*** Running vivado
    with args -log minized_sbc_base_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source minized_sbc_base_wrapper.tcl -notrace


****** Vivado v2021.1 (64-bit)
  **** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
  **** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source minized_sbc_base_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ealbertos/git/avnet/hdl/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2021.1/data/ip'.
add_files: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2599.250 ; gain = 16.027 ; free physical = 5719 ; free virtual = 7315
Command: link_design -top minized_sbc_base_wrapper -part xc7z007sclg225-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z007sclg225-1
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0.dcp' for cell 'minized_sbc_base_i/axi_gpio_0'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0.dcp' for cell 'minized_sbc_base_i/axi_gpio_1'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0.dcp' for cell 'minized_sbc_base_i/axi_gpio_2'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_iic_0_0/minized_sbc_base_axi_iic_0_0.dcp' for cell 'minized_sbc_base_i/axi_iic_0'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0.dcp' for cell 'minized_sbc_base_i/axi_intc_0'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0.dcp' for cell 'minized_sbc_base_i/bluetooth_uart'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.dcp' for cell 'minized_sbc_base_i/clk_wiz_0'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_led_mgr_0_0/minized_sbc_base_led_mgr_0_0.dcp' for cell 'minized_sbc_base_i/led_mgr_0'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_microphone_mgr_0_0/minized_sbc_base_microphone_mgr_0_0.dcp' for cell 'minized_sbc_base_i/microphone_mgr_0'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/minized_sbc_base_pdm_filt_0_0.dcp' for cell 'minized_sbc_base_i/pdm_filt_0'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_100MHz'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_142MHz'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_166MHz'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_200MHz'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_41MHz'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0.dcp' for cell 'minized_sbc_base_i/proc_sys_reset_50MHz'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.dcp' for cell 'minized_sbc_base_i/ps7'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_wireless_mgr_0_0/minized_sbc_base_wireless_mgr_0_0.dcp' for cell 'minized_sbc_base_i/wireless_mgr_0'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_xadc_wiz_0_0/minized_sbc_base_xadc_wiz_0_0.dcp' for cell 'minized_sbc_base_i/xadc_wiz_0'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_xbar_0/minized_sbc_base_xbar_0.dcp' for cell 'minized_sbc_base_i/ps7_axi_periph/xbar'
INFO: [Project 1-454] Reading design checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_auto_pc_0/minized_sbc_base_auto_pc_0.dcp' for cell 'minized_sbc_base_i/ps7_axi_periph/s00_couplers/auto_pc'
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00 . Memory (MB): peak = 2599.324 ; gain = 0.000 ; free physical = 5435 ; free virtual = 7031
INFO: [Netlist 29-17] Analyzing 80 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2021.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. minized_sbc_base_i/clk_wiz_0/inst/clkin1_ibufg 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_xadc_wiz_0_0/minized_sbc_base_xadc_wiz_0_0.xdc] for cell 'minized_sbc_base_i/xadc_wiz_0/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_xadc_wiz_0_0/minized_sbc_base_xadc_wiz_0_0.xdc] for cell 'minized_sbc_base_i/xadc_wiz_0/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.xdc] for cell 'minized_sbc_base_i/clk_wiz_0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.xdc:57]
get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2766.062 ; gain = 158.828 ; free physical = 4932 ; free virtual = 6543
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0.xdc] for cell 'minized_sbc_base_i/clk_wiz_0/inst'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0_board.xdc] for cell 'minized_sbc_base_i/clk_wiz_0/inst'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_clk_wiz_0_0/minized_sbc_base_clk_wiz_0_0_board.xdc] for cell 'minized_sbc_base_i/clk_wiz_0/inst'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_50MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_50MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_50MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_50MHz_0/minized_sbc_base_proc_sys_reset_50MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_50MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_41MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_41MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_41MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_41MHz_0/minized_sbc_base_proc_sys_reset_41MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_41MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_200MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_200MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_200MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_200MHz_0/minized_sbc_base_proc_sys_reset_200MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_200MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_166MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_166MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_166MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_166MHz_0/minized_sbc_base_proc_sys_reset_166MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_166MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_142MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_142MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_142MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_142MHz_0/minized_sbc_base_proc_sys_reset_142MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_142MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_100MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_100MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_100MHz/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_proc_sys_reset_100MHz_0/minized_sbc_base_proc_sys_reset_100MHz_0_board.xdc] for cell 'minized_sbc_base_i/proc_sys_reset_100MHz/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.xdc] for cell 'minized_sbc_base_i/ps7/inst'
WARNING: [Vivado 12-2489] -input_jitter contains time 0.187500 which will be rounded to 0.188 to ensure it is an integer multiple of 1 picosecond [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.xdc:21]
WARNING: [Vivado 12-2489] -input_jitter contains time 0.618750 which will be rounded to 0.619 to ensure it is an integer multiple of 1 picosecond [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.xdc:27]
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_ps7_0/minized_sbc_base_ps7_0.xdc] for cell 'minized_sbc_base_i/ps7/inst'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/constrs/pdm_filt.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/constrs/pdm_filt.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/pdm_filt_fir_compiler_v7_2_i0/constraints/fir_compiler_v7_2.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0/pdm_filt_struct/fir_7_2/pdm_filt_fir_compiler_v7_2_i0_instance/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/pdm_filt_fir_compiler_v7_2_i0/constraints/fir_compiler_v7_2.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0/pdm_filt_struct/fir_7_2/pdm_filt_fir_compiler_v7_2_i0_instance/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/pdm_filt_fir_compiler_v7_2_i1/constraints/fir_compiler_v7_2.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0/pdm_filt_struct/fir_7_2_1/pdm_filt_fir_compiler_v7_2_i1_instance/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_pdm_filt_0_0/pdm_filt_fir_compiler_v7_2_i1/constraints/fir_compiler_v7_2.xdc] for cell 'minized_sbc_base_i/pdm_filt_0/U0/pdm_filt_struct/fir_7_2_1/pdm_filt_fir_compiler_v7_2_i1_instance/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0.xdc] for cell 'minized_sbc_base_i/axi_intc_0/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0.xdc] for cell 'minized_sbc_base_i/axi_intc_0/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0.xdc] for cell 'minized_sbc_base_i/bluetooth_uart/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0.xdc] for cell 'minized_sbc_base_i/bluetooth_uart/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0_board.xdc] for cell 'minized_sbc_base_i/bluetooth_uart/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_uart16550_0_0/minized_sbc_base_axi_uart16550_0_0_board.xdc] for cell 'minized_sbc_base_i/bluetooth_uart/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_iic_0_0/minized_sbc_base_axi_iic_0_0_board.xdc] for cell 'minized_sbc_base_i/axi_iic_0/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_iic_0_0/minized_sbc_base_axi_iic_0_0_board.xdc] for cell 'minized_sbc_base_i/axi_iic_0/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_2/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_2/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_2/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_2_0/minized_sbc_base_axi_gpio_2_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_2/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_1/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_1/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_1/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_1_0/minized_sbc_base_axi_gpio_1_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_1/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0.xdc] for cell 'minized_sbc_base_i/axi_gpio_0/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_gpio_0_0/minized_sbc_base_axi_gpio_0_0_board.xdc] for cell 'minized_sbc_base_i/axi_gpio_0/U0'
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc]
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT0'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:70]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:70]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT0'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:71]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:71]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT1'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:74]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:74]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT1'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:75]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:75]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT2'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:78]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:78]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT2'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:79]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:79]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT3'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:82]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:82]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT3'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:83]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:83]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT4'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:86]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:86]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT4'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:87]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:87]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT5'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:90]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:90]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT5'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:91]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:91]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT6'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:94]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:94]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT6'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:95]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:95]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT7'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:98]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:98]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT7'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:99]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:99]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT8'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:105]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:105]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT8'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:106]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:106]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT9'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:109]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:109]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT9'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:110]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:110]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT10'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:113]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:113]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT10'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:114]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:114]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT11'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:117]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:117]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT11'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:118]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:118]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT12'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:121]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:121]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT12'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:122]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:122]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT13'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:125]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:125]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_DAT13'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:126]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:126]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR0'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:132]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:132]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR0'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:133]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:133]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR1'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:136]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:136]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR1'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:137]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:137]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR2'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:140]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:140]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'ARD_ADDR2'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:141]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:141]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_1_sda_io'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:179]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:179]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_1_sda_io'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:180]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:180]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_1_scl_io'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:182]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:182]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_1_scl_io'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:183]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:183]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_2_sda_io'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:186]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:186]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_2_sda_io'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:187]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:187]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_2_scl_io'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:189]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:189]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'iic_rtl_2_scl_io'. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:190]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc:190]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/minized_sbc_base.xdc]
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/bitstream_compression_enable.xdc]
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.srcs/constrs_1/imports/base/bitstream_compression_enable.xdc]
Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0_clocks.xdc] for cell 'minized_sbc_base_i/axi_intc_0/U0'
Finished Parsing XDC File [/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.gen/sources_1/bd/minized_sbc_base/ip/minized_sbc_base_axi_intc_0_0/minized_sbc_base_axi_intc_0_0_clocks.xdc] for cell 'minized_sbc_base_i/axi_intc_0/U0'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2782.113 ; gain = 0.000 ; free physical = 4927 ; free virtual = 6542
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 11 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 7 instances
  RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 4 instances

33 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2782.113 ; gain = 182.863 ; free physical = 4927 ; free virtual = 6542
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2810.953 ; gain = 28.840 ; free physical = 4915 ; free virtual = 6530

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 197c1408c

Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2823.828 ; gain = 12.875 ; free physical = 4915 ; free virtual = 6530

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 206adfd18

Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.40 . Memory (MB): peak = 2981.797 ; gain = 0.000 ; free physical = 4745 ; free virtual = 6360
INFO: [Opt 31-389] Phase Retarget created 109 cells and removed 181 cells
INFO: [Opt 31-1021] In phase Retarget, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1a4e76330

Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2981.797 ; gain = 0.000 ; free physical = 4745 ; free virtual = 6360
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 14 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 1f8a9897d

Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2981.797 ; gain = 0.000 ; free physical = 4744 ; free virtual = 6359
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1508 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1f8a9897d

Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:00.89 . Memory (MB): peak = 2981.797 ; gain = 0.000 ; free physical = 4744 ; free virtual = 6359
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 1f8a9897d

Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.91 . Memory (MB): peak = 2981.797 ; gain = 0.000 ; free physical = 4744 ; free virtual = 6359
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1f8a9897d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.96 . Memory (MB): peak = 2981.797 ; gain = 0.000 ; free physical = 4744 ; free virtual = 6359
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |             109  |             181  |                                              2  |
|  Constant propagation         |               0  |              14  |                                              0  |
|  Sweep                        |               0  |            1508  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2981.797 ; gain = 0.000 ; free physical = 4744 ; free virtual = 6359
Ending Logic Optimization Task | Checksum: 24579fd8d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2981.797 ; gain = 0.000 ; free physical = 4744 ; free virtual = 6359

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 4 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 8
Ending PowerOpt Patch Enables Task | Checksum: 24579fd8d

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3203.875 ; gain = 0.000 ; free physical = 4726 ; free virtual = 6346
Ending Power Optimization Task | Checksum: 24579fd8d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 3203.875 ; gain = 222.078 ; free physical = 4732 ; free virtual = 6351

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 24579fd8d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3203.875 ; gain = 0.000 ; free physical = 4732 ; free virtual = 6351

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3203.875 ; gain = 0.000 ; free physical = 4732 ; free virtual = 6351
Ending Netlist Obfuscation Task | Checksum: 24579fd8d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3203.875 ; gain = 0.000 ; free physical = 4732 ; free virtual = 6351
INFO: [Common 17-83] Releasing license: Implementation
56 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3203.875 ; gain = 421.762 ; free physical = 4732 ; free virtual = 6351
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3203.875 ; gain = 0.000 ; free physical = 4722 ; free virtual = 6344
INFO: [Common 17-1381] The checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file minized_sbc_base_wrapper_drc_opted.rpt -pb minized_sbc_base_wrapper_drc_opted.pb -rpx minized_sbc_base_wrapper_drc_opted.rpx
Command: report_drc -file minized_sbc_base_wrapper_drc_opted.rpt -pb minized_sbc_base_wrapper_drc_opted.pb -rpx minized_sbc_base_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4687 ; free virtual = 6312
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15c6cfb37

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4687 ; free virtual = 6312
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4687 ; free virtual = 6312

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12709d400

Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.95 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4695 ; free virtual = 6324

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 13d924a19

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4696 ; free virtual = 6326

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 13d924a19

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4696 ; free virtual = 6326
Phase 1 Placer Initialization | Checksum: 13d924a19

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4696 ; free virtual = 6327

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1abc293c4

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4694 ; free virtual = 6325

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 12021e04f

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4694 ; free virtual = 6325

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 12021e04f

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4694 ; free virtual = 6325

Phase 2.4 Global Placement Core

Phase 2.4.1 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 136 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 53 nets or LUTs. Breaked 0 LUT, combined 53 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4682 ; free virtual = 6315

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             53  |                    53  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             53  |                    53  |           0  |           4  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.1 Physical Synthesis In Placer | Checksum: 12cf06ef6

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4681 ; free virtual = 6315
Phase 2.4 Global Placement Core | Checksum: fb4104b9

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4681 ; free virtual = 6316
Phase 2 Global Placement | Checksum: fb4104b9

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4681 ; free virtual = 6316

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: a34d7df1

Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4681 ; free virtual = 6315

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 15f40b061

Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4680 ; free virtual = 6315

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 146a48494

Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4680 ; free virtual = 6315

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 14819c1d5

Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4680 ; free virtual = 6315

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 192b8ad89

Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4677 ; free virtual = 6313

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1c531bde6

Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4677 ; free virtual = 6313

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 15c80631d

Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4677 ; free virtual = 6313
Phase 3 Detail Placement | Checksum: 15c80631d

Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4677 ; free virtual = 6313

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1879315e2

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.981 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 19e1dc1a8

Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: 1d62cd824

Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309
Phase 4.1.1.1 BUFG Insertion | Checksum: 1879315e2

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.981. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 19d0d4fd4

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309
Phase 4.1 Post Commit Optimization | Checksum: 19d0d4fd4

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 19d0d4fd4

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                1x1|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 19d0d4fd4

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309
Phase 4.3 Placer Reporting | Checksum: 19d0d4fd4

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b46e1aaf

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309
Ending Placer Task | Checksum: 10480a0a9

Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4674 ; free virtual = 6309
INFO: [Common 17-83] Releasing license: Implementation
91 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4677 ; free virtual = 6313
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4661 ; free virtual = 6304
INFO: [Common 17-1381] The checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file minized_sbc_base_wrapper_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.37 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4666 ; free virtual = 6305
INFO: [runtcl-4] Executing : report_utilization -file minized_sbc_base_wrapper_utilization_placed.rpt -pb minized_sbc_base_wrapper_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file minized_sbc_base_wrapper_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4671 ; free virtual = 6309
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
101 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4642 ; free virtual = 6288
INFO: [Common 17-1381] The checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_physopt.dcp' has been generated.
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
Checksum: PlaceDB: d2825690 ConstDB: 0 ShapeSum: 31fe4a19 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 18c8a0d25

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4584 ; free virtual = 6226
Post Restoration Checksum: NetGraph: e45a3009 NumContArr: a82fdd1c Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 18c8a0d25

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4583 ; free virtual = 6226

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 18c8a0d25

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4567 ; free virtual = 6210

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 18c8a0d25

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4567 ; free virtual = 6210
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1661e1b8d

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4557 ; free virtual = 6201
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.882  | TNS=0.000  | WHS=-0.324 | THS=-73.049|

Phase 2 Router Initialization | Checksum: 2158922c0

Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6199

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00337838 %
  Global Horizontal Routing Utilization  = 0.00689338 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 3909
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 3908
  Number of Partially Routed Nets     = 1
  Number of Node Overlaps             = 0


Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2158922c0

Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6199
Phase 3 Initial Routing | Checksum: 1f7284d9b

Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 319
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.458  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 24a84c9ff

Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.458  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 1f61736db

Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200
Phase 4 Rip-up And Reroute | Checksum: 1f61736db

Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1f61736db

Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1f61736db

Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200
Phase 5 Delay and Skew Optimization | Checksum: 1f61736db

Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1bf258a47

Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.573  | TNS=0.000  | WHS=0.034  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1f5e70e75

Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200
Phase 6 Post Hold Fix | Checksum: 1f5e70e75

Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.73381 %
  Global Horizontal Routing Utilization  = 2.09053 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 18537f801

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6200

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 18537f801

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6199

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 14ffed1df

Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4555 ; free virtual = 6199

Phase 10 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=2.571  | TNS=0.000  | WHS=0.034  | THS=0.000  |

Phase 10 Post Router Timing | Checksum: 17acc9b89

Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4554 ; free virtual = 6199
INFO: [Route 35-61] The design met the timing requirement.
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4605 ; free virtual = 6250

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
117 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4605 ; free virtual = 6250
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3214.891 ; gain = 0.000 ; free physical = 4586 ; free virtual = 6240
INFO: [Common 17-1381] The checkpoint '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file minized_sbc_base_wrapper_drc_routed.rpt -pb minized_sbc_base_wrapper_drc_routed.pb -rpx minized_sbc_base_wrapper_drc_routed.rpx
Command: report_drc -file minized_sbc_base_wrapper_drc_routed.rpt -pb minized_sbc_base_wrapper_drc_routed.pb -rpx minized_sbc_base_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file minized_sbc_base_wrapper_methodology_drc_routed.rpt -pb minized_sbc_base_wrapper_methodology_drc_routed.pb -rpx minized_sbc_base_wrapper_methodology_drc_routed.rpx
Command: report_methodology -file minized_sbc_base_wrapper_methodology_drc_routed.rpt -pb minized_sbc_base_wrapper_methodology_drc_routed.pb -rpx minized_sbc_base_wrapper_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 4 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/impl_1/minized_sbc_base_wrapper_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file minized_sbc_base_wrapper_power_routed.rpt -pb minized_sbc_base_wrapper_power_summary_routed.pb -rpx minized_sbc_base_wrapper_power_routed.rpx
Command: report_power -file minized_sbc_base_wrapper_power_routed.rpt -pb minized_sbc_base_wrapper_power_summary_routed.pb -rpx minized_sbc_base_wrapper_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
130 Infos, 91 Warnings, 42 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file minized_sbc_base_wrapper_route_status.rpt -pb minized_sbc_base_wrapper_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file minized_sbc_base_wrapper_timing_summary_routed.rpt -pb minized_sbc_base_wrapper_timing_summary_routed.pb -rpx minized_sbc_base_wrapper_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file minized_sbc_base_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file minized_sbc_base_wrapper_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file minized_sbc_base_wrapper_bus_skew_routed.rpt -pb minized_sbc_base_wrapper_bus_skew_routed.pb -rpx minized_sbc_base_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
Command: write_bitstream -force minized_sbc_base_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 10249504 bits.
Writing bitstream ./minized_sbc_base_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [#UNDEF] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Fri Jul 14 18:44:58 2023. For additional details about this file, please refer to the WebTalk help file at /tools/Xilinx/Vivado/2021.1/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 3456.125 ; gain = 241.234 ; free physical = 4557 ; free virtual = 6217
INFO: [Common 17-206] Exiting Vivado at Fri Jul 14 18:44:58 2023...
[Fri Jul 14 18:44:59 2023] impl_1 finished
wait_on_run: Time (s): cpu = 00:18:51 ; elapsed = 00:25:25 . Memory (MB): peak = 2637.051 ; gain = 0.000 ; free physical = 6106 ; free virtual = 7785

***** Open the implemented design...
Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2637.051 ; gain = 0.000 ; free physical = 6033 ; free virtual = 7761
INFO: [Netlist 29-17] Analyzing 80 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2021.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_dir' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_from_Zynq' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_CMD_to_Zynq' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_dir[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_from_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'minized_sbc_base_i/wireless_mgr_0/SDIO_DATA_to_Zynq[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:07 . Memory (MB): peak = 3030.844 ; gain = 6.938 ; free physical = 5417 ; free virtual = 7237
Restored from archive | CPU: 0.820000 secs | Memory: 6.142982 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:07 . Memory (MB): peak = 3030.844 ; gain = 6.938 ; free physical = 5417 ; free virtual = 7237
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3174.957 ; gain = 0.000 ; free physical = 5415 ; free virtual = 7236
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 11 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 7 instances
  RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 4 instances

open_run: Time (s): cpu = 00:00:19 ; elapsed = 00:01:55 . Memory (MB): peak = 3174.957 ; gain = 537.906 ; free physical = 5415 ; free virtual = 7237

***** Write and validate the design archive...
WARNING: [Project 1-971] Hardware Platform (Shell) metadata attributes vendor, board, name, version will be populated from project properties platform.vendor (em.avnet.com), platform.board_id (minized_sbc_base), platform.name (minized_sbc_base) and platform.version (1.0). The values from PFM_NAME property (em.avnet.com:av:minized_sbc_base:1.0) on the BD will be over-ridden.
INFO: [Vivado 12-4895] Creating Hardware Platform: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.xsa ...
INFO: [Hsi 55-2053] elapsed time for repository (/tools/Xilinx/Vivado/2021.1/data/embeddedsw) loading 3 seconds
WARNING: [BD 41-2589] Platform should have atleast one axi memory mapped master interface. Enable a master AXI interface as platform AXI_PORT.
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:18 . Memory (MB): peak = 3214.422 ; gain = 0.000 ; free physical = 5205 ; free virtual = 7206
INFO: [Vivado 12-12466] The Hardware Platform can be used for Hardware and Hardware Emulation
INFO: [Vivado 12-4896] Successfully created Hardware Platform: /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.xsa
write_hw_platform: Time (s): cpu = 00:00:08 ; elapsed = 00:00:57 . Memory (MB): peak = 3214.422 ; gain = 39.465 ; free physical = 5155 ; free virtual = 7200
INFO: [Vivado 12-12082] Found metadata file: xsa.json
INFO: [Vivado 12-6078] Validating platform properties...
INFO: [Vivado 12-6079] Validating unified platform...
INFO: [Vivado 12-6073] Validating 'pre_synth' platform state...
INFO: [Vivado 12-6077] Validating platform files...
INFO: [Vivado 12-6067] Found file 'minized_sbc_base.bit' of type 'FULL_BIT' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'minized_sbc_base.hpfm' of type 'HPFM' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'prj/rebuild.tcl' of type 'REBUILD_TCL' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'prj/minized_sbc_base.srcs/sources_1/bd/minized_sbc_base/minized_sbc_base.bd' of type 'TOP_BD' in the Hardware Platform.
INFO: [Vivado 12-6066] Finished running validate_hw_platform for file: '/home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1/minized_sbc_base.xsa'

***** Close the implemented design...


*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Generating Binary...
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


Found End of Bitstream Creation...


*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Closing Project...
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


close_project: Time (s): cpu = 00:00:02 ; elapsed = 00:01:52 . Memory (MB): peak = 3214.422 ; gain = 0.000 ; free physical = 5206 ; free virtual = 7368


*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Not Running Tag
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*



Your Build Took
seconds [1947]

or a total of:

days [0]
hrs  [0]
min  [32]
sec  [27]

to complete

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-                                                     -*
*-            Finished Running Script                  -*
*-                                                     -*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

INFO: [Common 17-206] Exiting Vivado at Fri Jul 14 18:49:50 2023...

Creating 'minized_sbc_base_2021_1' Petalinux project ...

INFO: Create project: minized_sbc_base_2021_1
INFO: New project successfully created in /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1

Importing hardware definition minized_sbc_base.xsa from HDL project folder ...


Importing hardware bitstream minized_sbc_base_wrapper.bit from HDL project folder...

[INFO] Sourcing buildtools
INFO: Getting hardware description...
INFO: Renaming minized_sbc_base.xsa to system.xsa
[INFO] Generating Kconfig for project
[INFO] Silentconfig project
[INFO] Extracting yocto SDK to components/yocto. This may take time!
[INFO] Sourcing build environment
[INFO] Generating kconfig for Rootfs
[INFO] Silentconfig rootfs
[INFO] Generating plnxtool conf
[INFO] Adding user layers
[INFO] Generating workspace directory

Patching PetaLinux project config ...


Tag 2021p1_minized_sbc_20210426_105325 not found.  Cloning 2021.1 branch instead.


***WARNING:  This may result in build mismatch!***


Stop (<ctrl>-c) in the next 5 seconds if this is not OK. 

Pause here for 5 seconds
Clone meta-avnet layer and checkout 2021.1 branch

Cloning into 'project-spec/meta-avnet'...
remote: Enumerating objects: 4512, done.
remote: Counting objects: 100% (2282/2282), done.
remote: Compressing objects: 100% (947/947), done.
remote: Total 4512 (delta 1313), reused 1938 (delta 1227), pack-reused 2230
Receiving objects: 100% (4512/4512), 21.78 MiB | 9.31 MiB/s, done.
Resolving deltas: 100% (2332/2332), done.

Setting cache (sstate and download) path (/home/ealbertos/git/avnet/petalinux/projects/cache) ...

[INFO] Sourcing buildtools
[INFO] Silentconfig project
[INFO] Sourcing build environment
[INFO] Generating kconfig for Rootfs
[INFO] Silentconfig rootfs
[INFO] Generating plnxtool conf
[INFO] Adding user layers
[INFO] Generating workspace directory
[INFO] Successfully configured project

Modifying project config for INITRD boot support...

[INFO] Sourcing buildtools
[INFO] Silentconfig project
[INFO] Sourcing build environment
[INFO] Generating kconfig for Rootfs
[INFO] Silentconfig rootfs
[INFO] Generating plnxtool conf
[INFO] Generating workspace directory
[INFO] Successfully configured project

Building project...

[INFO] Sourcing buildtools
[INFO] Building avnet-image-full
[INFO] Sourcing build environment
[INFO] Generating workspace directory
INFO: bitbake avnet-image-full
NOTE: Started PRServer with DBfile: /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/build/cache/prserv.sqlite3, IP: 127.0.0.1, PORT: 38751, PID: 16999
Loading cache: 100% |                                                                                   | ETA:  --:--:--
Loaded 0 entries from dependency cache.
Parsing recipes: 100% |##################################################################################| Time: 0:03:10
Parsing of 3508 .bb files complete (0 cached, 3508 parsed). 5143 targets, 269 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
NOTE: Fetching uninative binary shim file:///home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/components/yocto/downloads/uninative/5ec5a9276046e7eceeac749a18b175667384e1f445cd4526300a41404d985a5b/x86_64-nativesdk-libc.tar.xz;sha256sum=5ec5a9276046e7eceeac749a18b175667384e1f445cd4526300a41404d985a5b (will check PREMIRRORS first)
Initialising tasks: 100% |###############################################################################| Time: 0:00:09
Checking sstate mirror object availability: 100% |#######################################################| Time: 0:02:46
Sstate summary: Wanted 2117 Found 0 Missed 2117 Current 0 (0% match, 0% complete)
NOTE: Executing Tasks
NOTE: Tasks Summary: Attempted 6285 tasks of which 10 didn't need to be rerun and all succeeded.
INFO: Successfully copied built images to tftp dir: /tftpboot
[INFO] Successfully built avnet-image-full
[INFO] Sourcing buildtools
INFO: Getting system flash information...
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/zynq_fsbl.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/project-spec/hw-description/minized_sbc_base.bit"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/u-boot.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.dtb"
INFO: Generating Zynq binary package BOOT.BIN...


****** Xilinx Bootgen v2021.1
  **** Build date : May 28 2021-21:36:22
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.


[INFO]   : Bootimage generated successfully

INFO: Binary is ready.
[INFO] Sourcing buildtools
INFO: Getting system flash information...
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/zynq_fsbl.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.bit"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/u-boot.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.dtb"
INFO: Generating Zynq binary package BOOT.BIN...


****** Xilinx Bootgen v2021.1
  **** Build date : May 28 2021-21:36:22
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.


[INFO]   : Bootimage generated successfully

INFO: Binary is ready.

Modifying project config for INITRD boot support...

[INFO] Sourcing buildtools
[INFO] Silentconfig project
[INFO] Sourcing build environment
[INFO] Generating kconfig for Rootfs
[INFO] Silentconfig rootfs
[INFO] Generating plnxtool conf
[INFO] Generating workspace directory
[INFO] Successfully configured project

Building project...

[INFO] Sourcing buildtools
[INFO] Building avnet-image-full
[INFO] Sourcing build environment
[INFO] Generating workspace directory
INFO: bitbake avnet-image-full
NOTE: Started PRServer with DBfile: /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/build/cache/prserv.sqlite3, IP: 127.0.0.1, PORT: 37329, PID: 9157
Loading cache: 100% |                                                                                   | ETA:  --:--:--
Loaded 0 entries from dependency cache.
Parsing recipes: 100% |##################################################################################| Time: 0:02:34
Parsing of 3508 .bb files complete (0 cached, 3508 parsed). 5143 targets, 269 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |###############################################################################| Time: 0:00:09
Sstate summary: Wanted 484 Found 437 Missed 47 Current 1618 (90% match, 97% complete)
NOTE: Executing Tasks
NOTE: Tasks Summary: Attempted 6242 tasks of which 5528 didn't need to be rerun and all succeeded.
INFO: Successfully copied built images to tftp dir: /tftpboot
[INFO] Successfully built avnet-image-full
[INFO] Sourcing buildtools
INFO: Getting system flash information...
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/zynq_fsbl.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/project-spec/hw-description/minized_sbc_base.bit"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/u-boot.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.dtb"
INFO: Generating Zynq binary package BOOT.BIN...


****** Xilinx Bootgen v2021.1
  **** Build date : May 28 2021-21:36:22
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.


[INFO]   : Bootimage generated successfully

INFO: Binary is ready.
[INFO] Sourcing buildtools
INFO: Getting system flash information...
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/zynq_fsbl.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.bit"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/u-boot.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.dtb"
INFO: Generating Zynq binary package BOOT.BIN...


****** Xilinx Bootgen v2021.1
  **** Build date : May 28 2021-21:36:22
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.


[INFO]   : Bootimage generated successfully

INFO: Binary is ready.

Modifying project config for EXT4 boot support...

[INFO] Sourcing buildtools
[INFO] Silentconfig project
[INFO] Sourcing build environment
[INFO] Generating kconfig for Rootfs
[INFO] Silentconfig rootfs
[INFO] Generating plnxtool conf
[INFO] Generating workspace directory
[INFO] Successfully configured project

Building project...

[INFO] Sourcing buildtools
[INFO] Building avnet-image-full
[INFO] Sourcing build environment
[INFO] Generating workspace directory
INFO: bitbake avnet-image-full
NOTE: Started PRServer with DBfile: /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/build/cache/prserv.sqlite3, IP: 127.0.0.1, PORT: 39711, PID: 26218
Loading cache: 100% |                                                                                   | ETA:  --:--:--
Loaded 0 entries from dependency cache.
Parsing recipes: 100% |##################################################################################| Time: 0:02:26
Parsing of 3508 .bb files complete (0 cached, 3508 parsed). 5143 targets, 269 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |###############################################################################| Time: 0:00:07
Checking sstate mirror object availability: 100% |#######################################################| Time: 0:00:09
Sstate summary: Wanted 321 Found 219 Missed 102 Current 1836 (68% match, 95% complete)
NOTE: Executing Tasks
NOTE: Tasks Summary: Attempted 6450 tasks of which 5874 didn't need to be rerun and all succeeded.
^CINFO: Successfully copied built images to tftp dir: /tftpboot
[INFO] Successfully built avnet-image-full
[INFO] Sourcing buildtools
INFO: Getting system flash information...
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/zynq_fsbl.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/project-spec/hw-description/minized_sbc_base.bit"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/u-boot.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.dtb"
INFO: Generating Zynq binary package BOOT.BIN...


****** Xilinx Bootgen v2021.1
  **** Build date : May 28 2021-21:36:22
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.


[INFO]   : Bootimage generated successfully

INFO: Binary is ready.
[INFO] Sourcing buildtools
INFO: Getting system flash information...
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/zynq_fsbl.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.bit"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/u-boot.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.dtb"
INFO: Generating Zynq binary package BOOT.BIN...


****** Xilinx Bootgen v2021.1
  **** Build date : May 28 2021-21:36:22
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.


[INFO]   : Bootimage generated successfully

INFO: Binary is ready.

Packaging project...


****** Vivado v2021.1 (64-bit)
  **** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
  **** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source swap_bits.tcl
# write_cfgmem -format bin -interface spix1 -loadbit "up 0x0 ./images/linux/system.bit" -force ./images/linux/system.bit.bin
Command: write_cfgmem -format bin -interface spix1 -loadbit {up 0x0 ./images/linux/system.bit} -force ./images/linux/system.bit.bin
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile ./images/linux/system.bit
Memory size is calculated to be 1 MB
Writing file ./images/linux/system.bit.bin
Writing log file ./images/linux/system.bit.prm
===================================
Configuration Memory information
===================================
File Format        BIN
Interface          SPIX1
Size               1M
Start Address      0x00000000
End Address        0x000FFFFF

Addr1         Addr2         Date                    File(s)
0x00000000    0x000C3EF3    Jul 14 18:51:36 2023    ./images/linux/system.bit
0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully
INFO: [Common 17-206] Exiting Vivado at Fri Jul 14 23:30:31 2023...

Un-setting cache (sstate and download) path (/home/ealbertos/git/avnet/petalinux/projects/cache) ...

INFO: Cleaning pre-built folder
INFO: Updating software prebuilt
INFO: Installing software images
INFO: Pre-built directory is updated.
/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1
INFO: Target BSP "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1.bsp" will contain the following projects
INFO: PetaLinux project: /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1
INFO: Sourcing build environment
INFO: 	Copying /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/config.project
INFO: 	Copying /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/.petalinux
INFO: 	Copying /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/.gitignore
INFO: 	Copying /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/pre-built
INFO: 	Copying /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/project-spec
INFO: 	Copying /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/components
INFO: 	Copying hardware project /home/ealbertos/git/avnet/hdl/projects/minized_sbc_base_2021_1
INFO: Creating BSP
INFO: Generating package minized_sbc_base_2021_1.bsp...
INFO: BSP is ready
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/scripts$ 

Program Flash the PetaLinux image onto the MiniZed via QSPI

Reference: Minimal MiniZed PetaLinux - Lab 1

Once the petalinux project is created we will run the boot_qsi_INITRD_MINIMAL.sh script under petalinux/scripts/boot

Run the script from the petalinux project directory petalinux/projects/minized_sbc_base_2021_1/

The Minized must be in JTAG <BOOT> mode 

ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/projects$ ls
cache  minized_sbc_base_2021_1  minized_sbc_base_2021_1.bsp
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/projects$ cd minized_sbc_base_2021_1/
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/projects/minized_sbc_base_2021_1$ ../../scripts/boot/minized/boot_qspi_INITRD_MINIMAL.sh
[INFO] Sourcing buildtools
INFO: Getting system flash information...
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/zynq_fsbl.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.bit"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/u-boot.elf"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/system.dtb"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/image_INITRD_MINIMAL.ub"
INFO: File in BOOT BIN: "/home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/images/linux/avnet-boot/avnet_qspi.scr"
INFO: Generating Zynq binary package BOOT_LINUX_QSPI.BIN...


****** Xilinx Bootgen v2021.1
  **** Build date : May 28 2021-21:36:22
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.


[INFO]   : Bootimage generated successfully

INFO: Binary is ready.

****** Xilinx Program Flash
****** Program Flash v2021.1 (64-bit)
  **** SW Build 3246112 on 2021-06-09-14:19:56
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:localhost:3121
Attempting to launch hw_server at TCP:localhost:3121

Connected to hw_server @ TCP:localhost:3121

Retrieving Flash info...

Initialization done
Using default mini u-boot image file - /tools/Xilinx/Vitis/2021.1/data/xicom/cfgmem/uboot/zynq_qspi_x4_single.bin
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x000FA240 =====
READ: IO_PLL_CFG (0xF8000118) = 0x000FA240
===== mrd->addr=0xF8000108, data=0x00030008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x00030008
Info:  Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B


U-Boot 2021.01-08077-gfb43236 (May 17 2021 - 10:20:35 -0600)

Model: Zynq CSE QSPI SINGLE Board
DRAM:  256 KiB
WARNING: Caches not enabled
In:    dcc
Out:   dcc
Err:   dcc
Zynq> sf probe 0 0 0
SF: Detected n25q128a13 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Zynq> Sector size = 65536.
f probe 0 0 0
Performing Erase Operation...
sf erase 0 FD0000
SF: 16580608 bytes @ 0x0 Erased: OK
Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 30 sec.
Performing Program Operation...
0%...sf write FFFC0000 0 20000
device 0 offset 0x0, size 0x20000
SF: 131072 bytes @ 0x0 Written: OK
Zynq> sf write FFFC0000 20000 20000
device 0 offset 0x20000, size 0x20000
SF: 131072 bytes @ 0x20000 Written: OK
Zynq> sf write FFFC0000 40000 20000
device 0 offset 0x40000, size 0x20000
SF: 131072 bytes @ 0x40000 Written: OK
Zynq> sf write FFFC0000 60000 20000
device 0 offset 0x60000, size 0x20000
SF: 131072 bytes @ 0x60000 Written: OK
Zynq> sf write FFFC0000 80000 20000
device 0 offset 0x80000, size 0x20000
SF: 131072 bytes @ 0x80000 Written: OK
Zynq> sf write FFFC0000 A0000 20000
device 0 offset 0xa0000, size 0x20000
SF: 131072 bytes @ 0xa0000 Written: OK
Zynq> sf write FFFC0000 C0000 20000
device 0 offset 0xc0000, size 0x20000
SF: 131072 bytes @ 0xc0000 Written: OK
Zynq> sf write FFFC0000 E0000 20000
device 0 offset 0xe0000, size 0x20000
SF: 131072 bytes @ 0xe0000 Written: OK
Zynq> sf write FFFC0000 100000 20000
device 0 offset 0x100000, size 0x20000
SF: 131072 bytes @ 0x100000 Written: OK
Zynq> sf write FFFC0000 120000 20000
device 0 offset 0x120000, size 0x20000
SF: 131072 bytes @ 0x120000 Written: OK
Zynq> sf write FFFC0000 140000 20000
device 0 offset 0x140000, size 0x20000
SF: 131072 bytes @ 0x140000 Written: OK
Zynq> sf write FFFC0000 160000 20000
device 0 offset 0x160000, size 0x20000
SF: 131072 bytes @ 0x160000 Written: OK
Zynq> sf write FFFC0000 180000 20000
device 0 offset 0x180000, size 0x20000
SF: 131072 bytes @ 0x180000 Written: OK
Zynq> 10%...sf write FFFC0000 1A0000 20000
device 0 offset 0x1a0000, size 0x20000
SF: 131072 bytes @ 0x1a0000 Written: OK
Zynq> sf write FFFC0000 1C0000 20000
device 0 offset 0x1c0000, size 0x20000
SF: 131072 bytes @ 0x1c0000 Written: OK
Zynq> sf write FFFC0000 1E0000 20000
device 0 offset 0x1e0000, size 0x20000
SF: 131072 bytes @ 0x1e0000 Written: OK
Zynq> sf write FFFC0000 200000 20000
device 0 offset 0x200000, size 0x20000
SF: 131072 bytes @ 0x200000 Written: OK
Zynq> sf write FFFC0000 220000 20000
device 0 offset 0x220000, size 0x20000
SF: 131072 bytes @ 0x220000 Written: OK
Zynq> sf write FFFC0000 240000 20000
device 0 offset 0x240000, size 0x20000
SF: 131072 bytes @ 0x240000 Written: OK
Zynq> sf write FFFC0000 260000 20000
device 0 offset 0x260000, size 0x20000
SF: 131072 bytes @ 0x260000 Written: OK
Zynq> sf write FFFC0000 280000 20000
device 0 offset 0x280000, size 0x20000
SF: 131072 bytes @ 0x280000 Written: OK
Zynq> sf write FFFC0000 2A0000 20000
device 0 offset 0x2a0000, size 0x20000
SF: 131072 bytes @ 0x2a0000 Written: OK
Zynq> sf write FFFC0000 2C0000 20000
device 0 offset 0x2c0000, size 0x20000
SF: 131072 bytes @ 0x2c0000 Written: OK
Zynq> sf write FFFC0000 2E0000 20000
device 0 offset 0x2e0000, size 0x20000
SF: 131072 bytes @ 0x2e0000 Written: OK
Zynq> sf write FFFC0000 300000 20000
device 0 offset 0x300000, size 0x20000
SF: 131072 bytes @ 0x300000 Written: OK
Zynq> sf write FFFC0000 320000 20000
device 0 offset 0x320000, size 0x20000
SF: 131072 bytes @ 0x320000 Written: OK
Zynq> 20%...sf write FFFC0000 340000 20000
device 0 offset 0x340000, size 0x20000
SF: 131072 bytes @ 0x340000 Written: OK
Zynq> sf write FFFC0000 360000 20000
device 0 offset 0x360000, size 0x20000
SF: 131072 bytes @ 0x360000 Written: OK
Zynq> sf write FFFC0000 380000 20000
device 0 offset 0x380000, size 0x20000
SF: 131072 bytes @ 0x380000 Written: OK
Zynq> sf write FFFC0000 3A0000 20000
device 0 offset 0x3a0000, size 0x20000
SF: 131072 bytes @ 0x3a0000 Written: OK
Zynq> sf write FFFC0000 3C0000 20000
device 0 offset 0x3c0000, size 0x20000
SF: 131072 bytes @ 0x3c0000 Written: OK
Zynq> sf write FFFC0000 3E0000 20000
device 0 offset 0x3e0000, size 0x20000
SF: 131072 bytes @ 0x3e0000 Written: OK
Zynq> sf write FFFC0000 400000 20000
device 0 offset 0x400000, size 0x20000
SF: 131072 bytes @ 0x400000 Written: OK
Zynq> sf write FFFC0000 420000 20000
device 0 offset 0x420000, size 0x20000
SF: 131072 bytes @ 0x420000 Written: OK
Zynq> sf write FFFC0000 440000 20000
device 0 offset 0x440000, size 0x20000
SF: 131072 bytes @ 0x440000 Written: OK
Zynq> sf write FFFC0000 460000 20000
device 0 offset 0x460000, size 0x20000
SF: 131072 bytes @ 0x460000 Written: OK
Zynq> sf write FFFC0000 480000 20000
device 0 offset 0x480000, size 0x20000
SF: 131072 bytes @ 0x480000 Written: OK
Zynq> sf write FFFC0000 4A0000 20000
device 0 offset 0x4a0000, size 0x20000
SF: 131072 bytes @ 0x4a0000 Written: OK
Zynq> 30%...sf write FFFC0000 4C0000 20000
device 0 offset 0x4c0000, size 0x20000
SF: 131072 bytes @ 0x4c0000 Written: OK
Zynq> sf write FFFC0000 4E0000 20000
device 0 offset 0x4e0000, size 0x20000
SF: 131072 bytes @ 0x4e0000 Written: OK
Zynq> sf write FFFC0000 500000 20000
device 0 offset 0x500000, size 0x20000
SF: 131072 bytes @ 0x500000 Written: OK
Zynq> sf write FFFC0000 520000 20000
device 0 offset 0x520000, size 0x20000
SF: 131072 bytes @ 0x520000 Written: OK
Zynq> sf write FFFC0000 540000 20000
device 0 offset 0x540000, size 0x20000
SF: 131072 bytes @ 0x540000 Written: OK
Zynq> sf write FFFC0000 560000 20000
device 0 offset 0x560000, size 0x20000
SF: 131072 bytes @ 0x560000 Written: OK
Zynq> sf write FFFC0000 580000 20000
device 0 offset 0x580000, size 0x20000
SF: 131072 bytes @ 0x580000 Written: OK
Zynq> sf write FFFC0000 5A0000 20000
device 0 offset 0x5a0000, size 0x20000
SF: 131072 bytes @ 0x5a0000 Written: OK
Zynq> sf write FFFC0000 5C0000 20000
device 0 offset 0x5c0000, size 0x20000
SF: 131072 bytes @ 0x5c0000 Written: OK
Zynq> sf write FFFC0000 5E0000 20000
device 0 offset 0x5e0000, size 0x20000
SF: 131072 bytes @ 0x5e0000 Written: OK
Zynq> sf write FFFC0000 600000 20000
device 0 offset 0x600000, size 0x20000
SF: 131072 bytes @ 0x600000 Written: OK
Zynq> sf write FFFC0000 620000 20000
device 0 offset 0x620000, size 0x20000
SF: 131072 bytes @ 0x620000 Written: OK
Zynq> sf write FFFC0000 640000 20000
device 0 offset 0x640000, size 0x20000
SF: 131072 bytes @ 0x640000 Written: OK
Zynq> 40%...sf write FFFC0000 660000 20000
device 0 offset 0x660000, size 0x20000
SF: 131072 bytes @ 0x660000 Written: OK
Zynq> sf write FFFC0000 680000 20000
device 0 offset 0x680000, size 0x20000
SF: 131072 bytes @ 0x680000 Written: OK
Zynq> sf write FFFC0000 6A0000 20000
device 0 offset 0x6a0000, size 0x20000
SF: 131072 bytes @ 0x6a0000 Written: OK
Zynq> sf write FFFC0000 6C0000 20000
device 0 offset 0x6c0000, size 0x20000
SF: 131072 bytes @ 0x6c0000 Written: OK
Zynq> sf write FFFC0000 6E0000 20000
device 0 offset 0x6e0000, size 0x20000
SF: 131072 bytes @ 0x6e0000 Written: OK
Zynq> sf write FFFC0000 700000 20000
device 0 offset 0x700000, size 0x20000
SF: 131072 bytes @ 0x700000 Written: OK
Zynq> sf write FFFC0000 720000 20000
device 0 offset 0x720000, size 0x20000
SF: 131072 bytes @ 0x720000 Written: OK
Zynq> sf write FFFC0000 740000 20000
device 0 offset 0x740000, size 0x20000
SF: 131072 bytes @ 0x740000 Written: OK
Zynq> sf write FFFC0000 760000 20000
device 0 offset 0x760000, size 0x20000
SF: 131072 bytes @ 0x760000 Written: OK
Zynq> sf write FFFC0000 780000 20000
device 0 offset 0x780000, size 0x20000
SF: 131072 bytes @ 0x780000 Written: OK
Zynq> sf write FFFC0000 7A0000 20000
device 0 offset 0x7a0000, size 0x20000
SF: 131072 bytes @ 0x7a0000 Written: OK
Zynq> sf write FFFC0000 7C0000 20000
device 0 offset 0x7c0000, size 0x20000
SF: 131072 bytes @ 0x7c0000 Written: OK
Zynq> 50%...sf write FFFC0000 7E0000 20000
device 0 offset 0x7e0000, size 0x20000
SF: 131072 bytes @ 0x7e0000 Written: OK
Zynq> sf write FFFC0000 800000 20000
device 0 offset 0x800000, size 0x20000
SF: 131072 bytes @ 0x800000 Written: OK
Zynq> sf write FFFC0000 820000 20000
device 0 offset 0x820000, size 0x20000
SF: 131072 bytes @ 0x820000 Written: OK
Zynq> sf write FFFC0000 840000 20000
device 0 offset 0x840000, size 0x20000
SF: 131072 bytes @ 0x840000 Written: OK
Zynq> sf write FFFC0000 860000 20000
device 0 offset 0x860000, size 0x20000
SF: 131072 bytes @ 0x860000 Written: OK
Zynq> sf write FFFC0000 880000 20000
device 0 offset 0x880000, size 0x20000
SF: 131072 bytes @ 0x880000 Written: OK
Zynq> sf write FFFC0000 8A0000 20000
device 0 offset 0x8a0000, size 0x20000
SF: 131072 bytes @ 0x8a0000 Written: OK
Zynq> sf write FFFC0000 8C0000 20000
device 0 offset 0x8c0000, size 0x20000
SF: 131072 bytes @ 0x8c0000 Written: OK
Zynq> sf write FFFC0000 8E0000 20000
device 0 offset 0x8e0000, size 0x20000
SF: 131072 bytes @ 0x8e0000 Written: OK
Zynq> sf write FFFC0000 900000 20000
device 0 offset 0x900000, size 0x20000
SF: 131072 bytes @ 0x900000 Written: OK
Zynq> sf write FFFC0000 920000 20000
device 0 offset 0x920000, size 0x20000
SF: 131072 bytes @ 0x920000 Written: OK
Zynq> sf write FFFC0000 940000 20000
device 0 offset 0x940000, size 0x20000
SF: 131072 bytes @ 0x940000 Written: OK
Zynq> sf write FFFC0000 960000 20000
device 0 offset 0x960000, size 0x20000
SF: 131072 bytes @ 0x960000 Written: OK
Zynq> 60%...sf write FFFC0000 980000 20000
device 0 offset 0x980000, size 0x20000
SF: 131072 bytes @ 0x980000 Written: OK
Zynq> sf write FFFC0000 9A0000 20000
device 0 offset 0x9a0000, size 0x20000
SF: 131072 bytes @ 0x9a0000 Written: OK
Zynq> sf write FFFC0000 9C0000 20000
device 0 offset 0x9c0000, size 0x20000
SF: 131072 bytes @ 0x9c0000 Written: OK
Zynq> sf write FFFC0000 9E0000 20000
device 0 offset 0x9e0000, size 0x20000
SF: 131072 bytes @ 0x9e0000 Written: OK
Zynq> sf write FFFC0000 A00000 20000
device 0 offset 0xa00000, size 0x20000
SF: 131072 bytes @ 0xa00000 Written: OK
Zynq> sf write FFFC0000 A20000 20000
device 0 offset 0xa20000, size 0x20000
SF: 131072 bytes @ 0xa20000 Written: OK
Zynq> sf write FFFC0000 A40000 20000
device 0 offset 0xa40000, size 0x20000
SF: 131072 bytes @ 0xa40000 Written: OK
Zynq> sf write FFFC0000 A60000 20000
device 0 offset 0xa60000, size 0x20000
SF: 131072 bytes @ 0xa60000 Written: OK
Zynq> sf write FFFC0000 A80000 20000
device 0 offset 0xa80000, size 0x20000
SF: 131072 bytes @ 0xa80000 Written: OK
Zynq> sf write FFFC0000 AA0000 20000
device 0 offset 0xaa0000, size 0x20000
SF: 131072 bytes @ 0xaa0000 Written: OK
Zynq> sf write FFFC0000 AC0000 20000
device 0 offset 0xac0000, size 0x20000
SF: 131072 bytes @ 0xac0000 Written: OK
Zynq> sf write FFFC0000 AE0000 20000
device 0 offset 0xae0000, size 0x20000
SF: 131072 bytes @ 0xae0000 Written: OK
Zynq> sf write FFFC0000 B00000 20000
device 0 offset 0xb00000, size 0x20000
SF: 131072 bytes @ 0xb00000 Written: OK
Zynq> 70%...sf write FFFC0000 B20000 20000
device 0 offset 0xb20000, size 0x20000
SF: 131072 bytes @ 0xb20000 Written: OK
Zynq> sf write FFFC0000 B40000 20000
device 0 offset 0xb40000, size 0x20000
SF: 131072 bytes @ 0xb40000 Written: OK
Zynq> sf write FFFC0000 B60000 20000
device 0 offset 0xb60000, size 0x20000
SF: 131072 bytes @ 0xb60000 Written: OK
Zynq> sf write FFFC0000 B80000 20000
device 0 offset 0xb80000, size 0x20000
SF: 131072 bytes @ 0xb80000 Written: OK
Zynq> sf write FFFC0000 BA0000 20000
device 0 offset 0xba0000, size 0x20000
SF: 131072 bytes @ 0xba0000 Written: OK
Zynq> sf write FFFC0000 BC0000 20000
device 0 offset 0xbc0000, size 0x20000
SF: 131072 bytes @ 0xbc0000 Written: OK
Zynq> sf write FFFC0000 BE0000 20000
device 0 offset 0xbe0000, size 0x20000
SF: 131072 bytes @ 0xbe0000 Written: OK
Zynq> sf write FFFC0000 C00000 20000
device 0 offset 0xc00000, size 0x20000
SF: 131072 bytes @ 0xc00000 Written: OK
Zynq> sf write FFFC0000 C20000 20000
device 0 offset 0xc20000, size 0x20000
SF: 131072 bytes @ 0xc20000 Written: OK
Zynq> sf write FFFC0000 C40000 20000
device 0 offset 0xc40000, size 0x20000
SF: 131072 bytes @ 0xc40000 Written: OK
Zynq> sf write FFFC0000 C60000 20000
device 0 offset 0xc60000, size 0x20000
SF: 131072 bytes @ 0xc60000 Written: OK
Zynq> sf write FFFC0000 C80000 20000
device 0 offset 0xc80000, size 0x20000
SF: 131072 bytes @ 0xc80000 Written: OK
Zynq> 80%...sf write FFFC0000 CA0000 20000
device 0 offset 0xca0000, size 0x20000
SF: 131072 bytes @ 0xca0000 Written: OK
Zynq> sf write FFFC0000 CC0000 20000
device 0 offset 0xcc0000, size 0x20000
SF: 131072 bytes @ 0xcc0000 Written: OK
Zynq> sf write FFFC0000 CE0000 20000
device 0 offset 0xce0000, size 0x20000
SF: 131072 bytes @ 0xce0000 Written: OK
Zynq> sf write FFFC0000 D00000 20000
device 0 offset 0xd00000, size 0x20000
SF: 131072 bytes @ 0xd00000 Written: OK
Zynq> sf write FFFC0000 D20000 20000
device 0 offset 0xd20000, size 0x20000
SF: 131072 bytes @ 0xd20000 Written: OK
Zynq> sf write FFFC0000 D40000 20000
device 0 offset 0xd40000, size 0x20000
SF: 131072 bytes @ 0xd40000 Written: OK
Zynq> sf write FFFC0000 D60000 20000
device 0 offset 0xd60000, size 0x20000
SF: 131072 bytes @ 0xd60000 Written: OK
Zynq> sf write FFFC0000 D80000 20000
device 0 offset 0xd80000, size 0x20000
SF: 131072 bytes @ 0xd80000 Written: OK
Zynq> sf write FFFC0000 DA0000 20000
device 0 offset 0xda0000, size 0x20000
SF: 131072 bytes @ 0xda0000 Written: OK
Zynq> sf write FFFC0000 DC0000 20000
device 0 offset 0xdc0000, size 0x20000
SF: 131072 bytes @ 0xdc0000 Written: OK
Zynq> sf write FFFC0000 DE0000 20000
device 0 offset 0xde0000, size 0x20000
SF: 131072 bytes @ 0xde0000 Written: OK
Zynq> sf write FFFC0000 E00000 20000
device 0 offset 0xe00000, size 0x20000
SF: 131072 bytes @ 0xe00000 Written: OK
Zynq> sf write FFFC0000 E20000 20000
device 0 offset 0xe20000, size 0x20000
SF: 131072 bytes @ 0xe20000 Written: OK
Zynq> 90%...sf write FFFC0000 E40000 20000
device 0 offset 0xe40000, size 0x20000
SF: 131072 bytes @ 0xe40000 Written: OK
Zynq> sf write FFFC0000 E60000 20000
device 0 offset 0xe60000, size 0x20000
SF: 131072 bytes @ 0xe60000 Written: OK
Zynq> sf write FFFC0000 E80000 20000
device 0 offset 0xe80000, size 0x20000
SF: 131072 bytes @ 0xe80000 Written: OK
Zynq> sf write FFFC0000 EA0000 20000
device 0 offset 0xea0000, size 0x20000
SF: 131072 bytes @ 0xea0000 Written: OK
Zynq> sf write FFFC0000 EC0000 20000
device 0 offset 0xec0000, size 0x20000
SF: 131072 bytes @ 0xec0000 Written: OK
Zynq> sf write FFFC0000 EE0000 20000
device 0 offset 0xee0000, size 0x20000
SF: 131072 bytes @ 0xee0000 Written: OK
Zynq> sf write FFFC0000 F00000 20000
device 0 offset 0xf00000, size 0x20000
SF: 131072 bytes @ 0xf00000 Written: OK
Zynq> sf write FFFC0000 F20000 20000
device 0 offset 0xf20000, size 0x20000
SF: 131072 bytes @ 0xf20000 Written: OK
Zynq> sf write FFFC0000 F40000 20000
device 0 offset 0xf40000, size 0x20000
SF: 131072 bytes @ 0xf40000 Written: OK
Zynq> sf write FFFC0000 F60000 20000
device 0 offset 0xf60000, size 0x20000
SF: 131072 bytes @ 0xf60000 Written: OK
Zynq> sf write FFFC0000 F80000 20000
device 0 offset 0xf80000, size 0x20000
SF: 131072 bytes @ 0xf80000 Written: OK
Zynq> sf write FFFC0000 FA0000 20000
device 0 offset 0xfa0000, size 0x20000
SF: 131072 bytes @ 0xfa0000 Written: OK
Zynq> 100%
sf write FFFC0000 FC0000 12C
device 0 offset 0xfc0000, size 0x12c
SF: 300 bytes @ 0xfc0000 Written: OK
Zynq> Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 1152 sec.

Flash Operation Successful
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/projects/minized_sbc_base_2021_1$ ^C
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/projects/minized_sbc_base_2021_1$ 

Booting from Flash

Now we put the Minized dip swich to Flash <BOOT> and reset the minized. We have done!

U-Boot 2021.01 (Jun 01 2021 - 11:54:06 +0000)

CPU:   Zynq 7z007s
Silicon: v3.1
DRAM:  ECC disabled 512 MiB
Flash: 0 Bytes
NAND:  0 MiB
MMC:   mmc@e0100000: 0, mmc@e0101000: 1
Loading Environment from SPIFlash... SF: Detected n25q128a13 with page size 256                                                      Bytes, erase size 4 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    serial@e0001000
Out:   serial@e0001000
Err:   serial@e0001000
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SF: Detected n25q128a13 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
device 0 offset 0xfc0000, size 0x40000
SF: 262144 bytes @ 0xfc0000 Read: OK
QSPI: Trying to boot script at 3000000
## Executing script at 03000000
SF: Detected n25q128a13 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
device 0 offset 0x300000, size 0xcc0000
SF: 13369344 bytes @ 0x300000 Read: OK
## Loading kernel from FIT Image at 04000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel-1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x040000f8
     Data Size:    4829784 Bytes = 4.6 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00200000
     Entry Point:  0x00200000
     Hash algo:    sha256
     Hash value:   9664f7b75a6eb6df9b0cf54b11b38de4203412fa12e78126c1cff32d552ed                                                     5f1
   Verifying Hash Integrity ... sha256+ OK
## Loading ramdisk from FIT Image at 04000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'ramdisk-1' ramdisk subimage
     Description:  avnet-image-minimal
     Type:         RAMDisk Image
     Compression:  uncompressed
     Data Start:   0x044a1adc
     Data Size:    7894716 Bytes = 7.5 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: unavailable
     Entry Point:  unavailable
     Hash algo:    sha256
     Hash value:   05249404facea3d60cc3ba70d0e5ab0e6c90bbdf83ea4aefe63ddc78d1b2f                                                     194
   Verifying Hash Integrity ... sha256+ OK
## Loading fdt from FIT Image at 04000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'fdt-system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x0449b45c
     Data Size:    26040 Bytes = 25.4 KiB
     Architecture: ARM
     Hash algo:    sha256
     Hash value:   2a88a3b2dbfac09790195f39b8de3fdda08e2a8d3feb16a44214da9ce36dd                                                     2b0
   Verifying Hash Integrity ... sha256+ OK
   Booting using the fdt blob at 0x449b45c
   Loading Kernel Image
   Loading Ramdisk to 1e35e000, end 1eae56bc ... OK
   Loading Device Tree to 1e354000, end 1e35d5b7 ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 5.10.0-xilinx-v2021.1 (oe-user@oe-host) (arm-xilinx-linux-gnueabi-                                                     gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP PREEMPT Fri Jun 4 15:57:1                                                     6 UTC 2021
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: xlnx,zynq-7000
earlycon: cdns0 at MMIO 0xe0001000 (options '115200n8')
printk: bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x1f000000
Zone ranges:
  Normal   [mem 0x0000000000000000-0x000000001fffffff]
  HighMem  empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x000000001fffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]
percpu: Embedded 15 pages/cpu s32396 r8192 d20852 u61440
Built 1 zonelists, mobility grouping on.  Total pages: 129920
Kernel command line: console=ttyPS0,115200 earlycon root=/dev/ram0 rw
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 482716K/524288K available (7168K kernel code, 274K rwdata, 1868K rodata,                                                      1024K init, 171K bss, 25188K reserved, 16384K cma-reserved, 0K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu:    RCU event tracing is enabled.
rcu:    RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
        Trampoline variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
GIC physical location is 0xf8f01000
irq-xilinx: /amba_pl/interrupt-controller@41800000: num_irq=32, sw_irq=0, edge=0                                                     x1
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
random: get_random_bytes called from start_kernel+0x2c0/0x4a4 with crng_init=0
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025                                                     , max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.6                                                     6 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
missing device node for CPU 1
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: failed to boot: -1
smp: Brought up 1 node, 1 CPU
SMP: Total of 1 processors activated (666.66 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911                                                     2604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
thermal_sys: Registered thermal governor 'step_wise'
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
e0000000.serial: ttyPS1 at MMIO 0xe0000000 (irq = 33, base_baud = 6249999) is a                                                      xuartps
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 34, base_baud = 6249999) is a                                                      xuartps
printk: console [ttyPS0] enabled
printk: console [ttyPS0] enabled
printk: bootconsole [cdns0] disabled
printk: bootconsole [cdns0] disabled
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@l                                                     inux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
Bluetooth: Core ver 2.22
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
Bluetooth: L2CAP socket layer initialized
Bluetooth: SCO socket layer initialized
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes, linear)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 0 bytes, default 64
Trying to unpack rootfs image as initramfs...

Freeing initrd memory: 7712K
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
Initialise system trusted keyrings
workingset: timestamp_bits=14 max_order=17 bucket_order=3
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
Key type asymmetric registered
Asymmetric key parser 'x509' registered
io scheduler mq-deadline registered
io scheduler kyber registered
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
43c00000.serial: ttyS2 at MMIO 0x43c01000 (irq = 57, base_baud = 3000000) is a 16550A
brd: module loaded
loop: module loaded
spi-nor spi0.0: found n25q128a13, expected n25q128a11
spi-nor spi0.0: trying to lock already unlocked area
spi-nor spi0.0: n25q128a13 (16384 Kbytes)
4 fixed-partitions partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000300000 : "boot"
0x000000300000-0x000000fc0000 : "kernel"
0x000000fc0000-0x000001000000 : "bootenv"
0x000001000000-0x000001000000 : "spare"
mtd: partition "spare" is out of reach -- disabled
libphy: Fixed MDIO Bus: probed
CAN device driver interface
e1000e: Intel(R) PRO/1000 Network Driver
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
usbcore: registered new interface driver rtl8150
usbcore: registered new interface driver r8152
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 30
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
Bluetooth: HCI UART driver ver 2.3
Bluetooth: HCI UART protocol H4 registered
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
ledtrig-cpu: registered to indicate activity on CPUs
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=49
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
mmc0: SDHCI controller on e0101000.mmc [e0101000.mmc] using ADMA
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core
NET: Registered protocol family 29
can: raw protocol
can: broadcast manager protocol
can: netlink gateway - max_hops=1
Bluetooth: RFCOMM socket layer initialized
Bluetooth: RFCOMM ver 1.11
Bluetooth: BNEP (Ethernet Emulation) ver 1.3
Bluetooth: BNEP socket layer initialized
Bluetooth: HIDP (Human Interface Emulation) ver 1.2
Bluetooth: HIDP socket layer initialized
Registering SWP/SWPB emulation handler
Loading compiled-in X.509 certificates
of-fpga-region fpga-full: FPGA Region probed
of_cfs_init
of_cfs_init: OK
cfg80211: Loading compiled-in X.509 certificates for regulatory database
mmc0: new high speed MMC card at address 0001
mmc1: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
mmcblk0: mmc0:0001 Q2J55L 7.09 GiB
cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
ALSA device list:
mmcblk0boot0: mmc0:0001 Q2J55L partition 1 16.0 MiB
mmcblk0boot1: mmc0:0001 Q2J55L partition 2 16.0 MiB
  No soundcards found.
mmcblk0rpmb: mmc0:0001 Q2J55L partition 3 4.00 MiB, chardev (246:0)
Freeing unused kernel memory: 1024K
platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
Run /init as init process
cfg80211: failed to load regulatory.db
mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
INIT:  mmcblk0: p1
mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
version 2.97 bootingmmc1: queuing unknown CIS tuple 0x80 (3 bytes)
mmc1: queuing unknown CIS tuple 0x80 (6 bytes)

random: fast init done
mmc1: new high speed SDIO card at address 0001
Starting udev
udevd[99]: starting version 3.2.9
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
udevd[100]: starting eudev-3.2.9
brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43430-sdio for chip BCM43430/1
brcmfmac mmc1:0001:1: Direct firmware load for brcm/brcmfmac43430-sdio.bin failed with error -2
brcmfmac: brcmf_sdio_htclk: HT Avail timeout (1000000): clkctl 0x50
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
urandom_read: 1 callbacks suppressed
random: dd: uninitialized urandom read (512 bytes read)
random: crng init done

Installing Full Image of PetaLinux to eMMC

Once we have a minimal Petalinux image running on the MiniZed we can install a full image to eMMC from PetaLinux.

Reference: Install full featured PetaLinux - Lab 2

Copy the generated rootfs.wic and the wpa_supplicant.conf over a FAT or FAT32 USB flash drive.

You need to edit the wpa_supplicant.conf with your WIFI settings. Adam Taylor’s MicroZed Chronicles, Part 207: Setting up MiniZed WIFI and Bluetooth Connectivity (xilinx.com)

Disconnect your MiniZed board that has been previously programmed with the minimal PetaLinux QSPI image that we created previously.

While it’s powered off (USB cables removed), make sure the board is set to boot up in Flash <BOOT> mode (not JTAG).

Power the board with both USB ports connected, one for the UART and the other for powering the USB Host interface.

Open a terminal session from your PC and reboot the MiniZed by pressing the reset button (SW2, in the corner near the Pmod connector).

Plug your FAT/FAT32 USB Thumb Drive into the USB port on the MiniZed. This should show up as /dev/sda1

mkdir /mnt/usb
#mount /dev/sda1 /mnt/usb

apply the rootfs file system to the eMMC

umount /dev/mmcblk0*
dd if=/run/media/sda1/rootfs.wic of=/dev/mmcblk0

This takes a log time. When finished copy the boot script

cp /media/sd-mmcblk0p1/avnet-boot/avnet_emmc.scr /media/sdmmcblk0p1/boot.scr
parted /dev/mmcblk0 resizepart 2 100%
e2fsck -f /dev/mmcblk0p2
resize2fs /dev/mmcblk0p2

remove boot script on the qspi, so that u-boot will look for a boot script on the emmc.

flash_erase /dev/mtd2 0 0

Next step is rebooting the system.

shutdown -r now

root@minized-sbc-base-2021-1:/mnt/usb# shutdown -r now

@º,ZZ·$×t message from root@minized-sbc-base-2021-1 (ttyPS0) (Fri Mar  9 13:59:48 2018):
        W
         «WK²j?¨(Ê*
ÍÍ?½¹¥Õɲ¥z*?½J¹¥ÑÑU¹¥¹?¢¡¢I5¥¹±5jRüroot@minized-sbc-base-2021-1:/mnt/usb# Stopping haveged:

Stopping Dropbear SSH server: stopped /usr/sbin/dropbear (pid 513)
dropbear.
hwclock: can't open '/dev/misc/rtc': No such file or directory
Stopping internet superserver: inetd.
Stopping syslogd/klogd: stopped syslogd (pid 524)
stopped klogd (pid 527)
done
Stopping tcf-agent: OK
Deconfiguring network interfaces... ifdown: interface eth0 not configured
done.
Sending all processes the TERM signal...
Sending all processes the KILL signal...
Unmounting remote filesystems...
Deactivating swap...
Unmounting local filesystems...
Rebooting... reboot: Restarting system


U-Boot 2021.01 (Jun 01 2021 - 11:54:06 +0000)

CPU:   Zynq 7z007s
Silicon: v3.1
DRAM:  ECC disabled 512 MiB
Flash: 0 Bytes
NAND:  0 MiB
MMC:   mmc@e0100000: 0, mmc@e0101000: 1
Loading Environment from SPIFlash... SF: Detected n25q128a13 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    serial@e0001000
Out:   serial@e0001000
Err:   serial@e0001000
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SF: Detected n25q128a13 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
device 0 offset 0xfc0000, size 0x40000
SF: 262144 bytes @ 0xfc0000 Read: OK
QSPI: Trying to boot script at 3000000
## Executing script at 03000000
Wrong image format for "source" command
QSPI: SCRIPT FAILED: continuing...
JTAG: Trying to boot script at 3000000
## Executing script at 03000000
Wrong image format for "source" command
JTAG: SCRIPT FAILED: continuing...
Card did not respond to voltage select! : -110
switch to partitions #0, OK
mmc1(part 0) is current device
Scanning mmc 1:1...
Found U-Boot script /boot.scr
264 bytes read in 9 ms (28.3 KiB/s)
## Executing script at 03000000
4857732 bytes read in 282 ms (16.4 MiB/s)
## Loading kernel from FIT Image at 04000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel-1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x040000f8
     Data Size:    4829784 Bytes = 4.6 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00200000
     Entry Point:  0x00200000
     Hash algo:    sha256
     Hash value:   9664f7b75a6eb6df9b0cf54b11b38de4203412fa12e78126c1cff32d552ed5f1
   Verifying Hash Integrity ... sha256+ OK
## Loading fdt from FIT Image at 04000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'fdt-system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x0449b45c
     Data Size:    26052 Bytes = 25.4 KiB
     Architecture: ARM
     Hash algo:    sha256
     Hash value:   5dca4ce0ee8655573dfd81b03d1218ebc1004994811596295266d88fba320edd
   Verifying Hash Integrity ... sha256+ OK
   Booting using the fdt blob at 0x449b45c
   Loading Kernel Image
   Loading Device Tree to 1eadc000, end 1eae55c3 ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 5.10.0-xilinx-v2021.1 (oe-user@oe-host) (arm-xilinx-linux-gnueabi-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP PREEMPT Fri Jun 4 15:57:16 UTC 2021
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: xlnx,zynq-7000
earlycon: cdns0 at MMIO 0xe0001000 (options '115200n8')
printk: bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x1f000000
Zone ranges:
  Normal   [mem 0x0000000000000000-0x000000001fffffff]
  HighMem  empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x000000001fffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]
percpu: Embedded 15 pages/cpu s32396 r8192 d20852 u61440
Built 1 zonelists, mobility grouping on.  Total pages: 129920
Kernel command line: console=ttyPS0,115200 earlycon root=/dev/mmcblk0p2 rw rootwait
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 490432K/524288K available (7168K kernel code, 274K rwdata, 1868K rodata, 1024K init, 171K bss, 17472K reserved, 16384K cma-reserved, 0K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu:    RCU event tracing is enabled.
rcu:    RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
        Trampoline variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
GIC physical location is 0xf8f01000
irq-xilinx: /amba_pl/interrupt-controller@41800000: num_irq=32, sw_irq=0, edge=0x1
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
random: get_random_bytes called from start_kernel+0x2c0/0x4a4 with crng_init=0
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
missing device node for CPU 1
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: failed to boot: -1
smp: Brought up 1 node, 1 CPU
SMP: Total of 1 processors activated (666.66 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
thermal_sys: Registered thermal governor 'step_wise'
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
e0000000.serial: ttyPS1 at MMIO 0xe0000000 (irq = 33, base_baud = 6249999) is a xuartps
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 34, base_baud = 6249999) is a xuartps
printk: console [ttyPS0] enabled
printk: console [ttyPS0] enabled
printk: bootconsole [cdns0] disabled
printk: bootconsole [cdns0] disabled
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
Bluetooth: Core ver 2.22
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
Bluetooth: L2CAP socket layer initialized
Bluetooth: SCO socket layer initialized
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes, linear)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 0 bytes, default 64
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
Initialise system trusted keyrings
workingset: timestamp_bits=14 max_order=17 bucket_order=3
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
Key type asymmetric registered
Asymmetric key parser 'x509' registered
io scheduler mq-deadline registered
io scheduler kyber registered
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
43c00000.serial: ttyS2 at MMIO 0x43c01000 (irq = 57, base_baud = 3000000) is a 16550A
brd: module loaded
loop: module loaded
spi-nor spi0.0: found n25q128a13, expected n25q128a11
spi-nor spi0.0: trying to lock already unlocked area
spi-nor spi0.0: n25q128a13 (16384 Kbytes)
4 fixed-partitions partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000300000 : "boot"
0x000000300000-0x000000fc0000 : "kernel"
0x000000fc0000-0x000001000000 : "bootenv"
0x000001000000-0x000001000000 : "spare"
mtd: partition "spare" is out of reach -- disabled
libphy: Fixed MDIO Bus: probed
CAN device driver interface
e1000e: Intel(R) PRO/1000 Network Driver
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
usbcore: registered new interface driver rtl8150
usbcore: registered new interface driver r8152
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 30
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
Bluetooth: HCI UART driver ver 2.3
Bluetooth: HCI UART protocol H4 registered
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
ledtrig-cpu: registered to indicate activity on CPUs
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=49
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
mmc0: SDHCI controller on e0101000.mmc [e0101000.mmc] using ADMA
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core
NET: Registered protocol family 29
can: raw protocol
can: broadcast manager protocol
can: netlink gateway - max_hops=1
Bluetooth: RFCOMM socket layer initialized
Bluetooth: RFCOMM ver 1.11
Bluetooth: BNEP (Ethernet Emulation) ver 1.3
Bluetooth: BNEP socket layer initialized
Bluetooth: HIDP (Human Interface Emulation) ver 1.2
Bluetooth: HIDP socket layer initialized
Registering SWP/SWPB emulation handler
Loading compiled-in X.509 certificates
of-fpga-region fpga-full: FPGA Region probed
of_cfs_init
of_cfs_init: OK
cfg80211: Loading compiled-in X.509 certificates for regulatory database
cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
ALSA device list:
  No soundcards found.
cfg80211: failed to load regulatory.db
mmc0: new high speed MMC card at address 0001
mmc1: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
mmcblk0: mmc0:0001 Q2J55L 7.09 GiB
mmcblk0boot0: mmc0:0001 Q2J55L partition 1 16.0 MiB
mmcblk0boot1: mmc0:0001 Q2J55L partition 2 16.0 MiB
mmcblk0rpmb: mmc0:0001 Q2J55L partition 3 4.00 MiB, chardev (246:0)
 mmcblk0: p1 p2
mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
devtmpfs: mounted
Freeing unused kernel memory: 1024K
Run /sbin/init as init process
mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
mmc1: queuing unknown CIS tuple 0x80 (6 bytes)
random: fast init done
INIT: usb 1-1: new high-speed USB device number 2 using ci_hdrc
version 2.97 bootingmmc1: new high speed SDIO card at address 0001

usb-storage 1-1:1.0: USB Mass Storage device detected
scsi host0: usb-storage 1-1:1.0
Starting udev
udevd[102]: starting version 3.2.9
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
udevd[103]: starting eudev-3.2.9
lis2ds_core: loading out-of-tree module taints kernel.
input: ST LIS2DS Accelerometer Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input0
[drm] Probing for xlnx,zocl
zocl-drm amba_pl:zyxclmm_drm: IRQ index 32 not found
input: ST LIS2DS Step Counter Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input1
[drm] PR Isolation addr 0x0
[drm] Initialized zocl 0.0.0 -1061020 for amba_pl:zyxclmm_drm on minor 0
input: ST LIS2DS Free Fall Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input2
input: ST LIS2DS Tap Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input3
brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43430-sdio for chip BCM43430/1
input: ST LIS2DS Double Tap Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input4
brcmfmac mmc1:0001:1: Direct firmware load for brcm/brcmfmac43430-sdio.xlnx,zynq-7000.txt failed with error -2
input: ST LIS2DS Step Detector Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input5
scsi 0:0:0:0: Direct-Access     Kingston DataTraveler 2.0 PMAP PQ: 0 ANSI: 0 CCS
sd 0:0:0:0: [sda] 8060928 512-byte logical blocks: (4.13 GB/3.84 GiB)
sd 0:0:0:0: Attached scsi generic sg0 type 0
input: ST LIS2DS Tilt Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input6
sd 0:0:0:0: [sda] Write Protect is off
brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43430-sdio for chip BCM43430/1
sd 0:0:0:0: [sda] No Caching mode page found
input: ST LIS2DS Significant Motion Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input7
sd 0:0:0:0: [sda] Assuming drive cache: write through
brcmfmac: brcmf_c_preinit_dcmds: Firmware: BCM43430/1 wl0: Feb  7 2018 06:14:09 version 7.45.98.45 (r683668 CY) FWID 01-56a4902c
input: ST LIS2DS Wake Up Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input8
 sda: sda1
sd 0:0:0:0: [sda] Attached SCSI removable disk
input: ST LIS2DS Activity Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input9
lis2ds 1-001d: lis2ds: probed
FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
zocl-drm amba_pl:zyxclmm_drm: IRQ index 32 not found
Starting tcf-agent: OK

PetaLinux 2021.1 minized-sbc-base-2021-1 ttyPS0


root@minized-sbc-base-2021-1:~# 

Connect MiniZed to a LAN with Wi-Fi

After all these magic recipes and the occasional spell, we can now connect our MiniZed to a LAN via WiFi.

U-Boot 2021.01 (Jun 01 2021 - 11:54:06 +0000)

CPU:   Zynq 7z007s
Silicon: v3.1
DRAM:  ECC disabled 512 MiB
Flash: 0 Bytes
NAND:  0 MiB
MMC:   mmc@e0100000: 0, mmc@e0101000: 1
Loading Environment from SPIFlash... SF: Detected n25q128a13 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    serial@e0001000
Out:   serial@e0001000
Err:   serial@e0001000
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SF: Detected n25q128a13 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
device 0 offset 0xfc0000, size 0x40000
SF: 262144 bytes @ 0xfc0000 Read: OK
QSPI: Trying to boot script at 3000000
## Executing script at 03000000
Wrong image format for "source" command
QSPI: SCRIPT FAILED: continuing...
JTAG: Trying to boot script at 3000000
## Executing script at 03000000
Wrong image format for "source" command
JTAG: SCRIPT FAILED: continuing...
Card did not respond to voltage select! : -110
switch to partitions #0, OK
mmc1(part 0) is current device
Scanning mmc 1:1...
Found U-Boot script /boot.scr
264 bytes read in 9 ms (28.3 KiB/s)
## Executing script at 03000000
4857732 bytes read in 282 ms (16.4 MiB/s)
## Loading kernel from FIT Image at 04000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel-1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x040000f8
     Data Size:    4829784 Bytes = 4.6 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00200000
     Entry Point:  0x00200000
     Hash algo:    sha256
     Hash value:   9664f7b75a6eb6df9b0cf54b11b38de4203412fa12e78126c1cff32d552ed5f1
   Verifying Hash Integrity ... sha256+ OK
## Loading fdt from FIT Image at 04000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'fdt-system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x0449b45c
     Data Size:    26052 Bytes = 25.4 KiB
     Architecture: ARM
     Hash algo:    sha256
     Hash value:   5dca4ce0ee8655573dfd81b03d1218ebc1004994811596295266d88fba320edd
   Verifying Hash Integrity ... sha256+ OK
   Booting using the fdt blob at 0x449b45c
   Loading Kernel Image
   Loading Device Tree to 1eadc000, end 1eae55c3 ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 5.10.0-xilinx-v2021.1 (oe-user@oe-host) (arm-xilinx-linux-gnueabi-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP PREEMPT Fri Jun 4 15:57:16 UTC 2021
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: xlnx,zynq-7000
earlycon: cdns0 at MMIO 0xe0001000 (options '115200n8')
printk: bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x1f000000
Zone ranges:
  Normal   [mem 0x0000000000000000-0x000000001fffffff]
  HighMem  empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x000000001fffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]
percpu: Embedded 15 pages/cpu s32396 r8192 d20852 u61440
Built 1 zonelists, mobility grouping on.  Total pages: 129920
Kernel command line: console=ttyPS0,115200 earlycon root=/dev/mmcblk0p2 rw rootwait
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 490432K/524288K available (7168K kernel code, 274K rwdata, 1868K rodata, 1024K init, 171K bss, 17472K reserved, 16384K cma-reserved, 0K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu:    RCU event tracing is enabled.
rcu:    RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
        Trampoline variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
GIC physical location is 0xf8f01000
irq-xilinx: /amba_pl/interrupt-controller@41800000: num_irq=32, sw_irq=0, edge=0x1
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
random: get_random_bytes called from start_kernel+0x2c0/0x4a4 with crng_init=0
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
missing device node for CPU 1
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: failed to boot: -1
smp: Brought up 1 node, 1 CPU
SMP: Total of 1 processors activated (666.66 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
thermal_sys: Registered thermal governor 'step_wise'
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
e0000000.serial: ttyPS1 at MMIO 0xe0000000 (irq = 33, base_baud = 6249999) is a xuartps
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 34, base_baud = 6249999) is a xuartps
printk: console [ttyPS0] enabled
printk: console [ttyPS0] enabled
printk: bootconsole [cdns0] disabled
printk: bootconsole [cdns0] disabled
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
Bluetooth: Core ver 2.22
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
Bluetooth: L2CAP socket layer initialized
Bluetooth: SCO socket layer initialized
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes, linear)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 0 bytes, default 64
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
Initialise system trusted keyrings
workingset: timestamp_bits=14 max_order=17 bucket_order=3
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
Key type asymmetric registered
Asymmetric key parser 'x509' registered
io scheduler mq-deadline registered
io scheduler kyber registered
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
43c00000.serial: ttyS2 at MMIO 0x43c01000 (irq = 57, base_baud = 3000000) is a 16550A
brd: module loaded
loop: module loaded
spi-nor spi0.0: found n25q128a13, expected n25q128a11
spi-nor spi0.0: trying to lock already unlocked area
spi-nor spi0.0: n25q128a13 (16384 Kbytes)
4 fixed-partitions partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000300000 : "boot"
0x000000300000-0x000000fc0000 : "kernel"
0x000000fc0000-0x000001000000 : "bootenv"
0x000001000000-0x000001000000 : "spare"
mtd: partition "spare" is out of reach -- disabled
libphy: Fixed MDIO Bus: probed
CAN device driver interface
e1000e: Intel(R) PRO/1000 Network Driver
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
usbcore: registered new interface driver rtl8150
usbcore: registered new interface driver r8152
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 30
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
Bluetooth: HCI UART driver ver 2.3
Bluetooth: HCI UART protocol H4 registered
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
ledtrig-cpu: registered to indicate activity on CPUs
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=49
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
mmc0: SDHCI controller on e0101000.mmc [e0101000.mmc] using ADMA
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core
NET: Registered protocol family 29
can: raw protocol
can: broadcast manager protocol
can: netlink gateway - max_hops=1
Bluetooth: RFCOMM socket layer initialized
Bluetooth: RFCOMM ver 1.11
Bluetooth: BNEP (Ethernet Emulation) ver 1.3
Bluetooth: BNEP socket layer initialized
Bluetooth: HIDP (Human Interface Emulation) ver 1.2
Bluetooth: HIDP socket layer initialized
Registering SWP/SWPB emulation handler
Loading compiled-in X.509 certificates
of-fpga-region fpga-full: FPGA Region probed
of_cfs_init
of_cfs_init: OK
cfg80211: Loading compiled-in X.509 certificates for regulatory database
cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
ALSA device list:
  No soundcards found.
cfg80211: failed to load regulatory.db
mmc0: new high speed MMC card at address 0001
mmc1: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
mmcblk0: mmc0:0001 Q2J55L 7.09 GiB
mmcblk0boot0: mmc0:0001 Q2J55L partition 1 16.0 MiB
mmcblk0boot1: mmc0:0001 Q2J55L partition 2 16.0 MiB
mmcblk0rpmb: mmc0:0001 Q2J55L partition 3 4.00 MiB, chardev (246:0)
 mmcblk0: p1 p2
mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
random: fast init done
mmc1: queuing unknown CIS tuple 0x80 (6 bytes)
EXT4-fs (mmcblk0p2): recovery complete
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel memory: 1024K
Run /sbin/init as init process
usb 1-1: new high-speed USB device number 2 using ci_hdrc
INIT: mmc1: new high speed SDIO card at address 0001
version 2.97 booting
usb-storage 1-1:1.0: USB Mass Storage device detected
scsi host0: usb-storage 1-1:1.0
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
Starting udev
udevd[102]: starting version 3.2.9
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
udevd[103]: starting eudev-3.2.9
zocl: loading out-of-tree module taints kernel.
input: ST LIS2DS Accelerometer Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input0
[drm] Probing for xlnx,zocl
zocl-drm amba_pl:zyxclmm_drm: IRQ index 32 not found
input: ST LIS2DS Step Counter Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input1
[drm] PR Isolation addr 0x0
[drm] Initialized zocl 0.0.0 -1061020 for amba_pl:zyxclmm_drm on minor 0
input: ST LIS2DS Free Fall Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input2
input: ST LIS2DS Tap Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input3
input: ST LIS2DS Double Tap Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input4
scsi 0:0:0:0: Direct-Access     Kingston DataTraveler 2.0 PMAP PQ: 0 ANSI: 0 CCS
brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43430-sdio for chip BCM43430/1
input: ST LIS2DS Step Detector Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input5
sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] 8060928 512-byte logical blocks: (4.13 GB/3.84 GiB)
sd 0:0:0:0: [sda] Write Protect is off
input: ST LIS2DS Tilt Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input6
brcmfmac mmc1:0001:1: Direct firmware load for brcm/brcmfmac43430-sdio.xlnx,zynq-7000.txt failed with error -2
sd 0:0:0:0: [sda] No Caching mode page found
sd 0:0:0:0: [sda] Assuming drive cache: write through
input: ST LIS2DS Significant Motion Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input7
 sda: sda1
sd 0:0:0:0: [sda] Attached SCSI removable disk
input: ST LIS2DS Wake Up Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input8
brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43430-sdio for chip BCM43430/1
input: ST LIS2DS Activity Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input9
brcmfmac: brcmf_c_preinit_dcmds: Firmware: BCM43430/1 wl0: Feb  7 2018 06:14:09 version 7.45.98.45 (r683668 CY) FWID 01-56a4902c
lis2ds 1-001d: lis2ds: probed
FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
Starting tcf-agent: OK

PetaLinux 2021.1 minized-sbc-base-2021-1 ttyPS0


root@minized-sbc-base-2021-1:~# wifi.sh
Copy the wpa_supplicant.conf file from eMMC to /etc.
NOTE!  This file must have been previously edited with
the WLAN SSID and password!
Mount the eMMC.
mount: /mnt: special device /dev/mmcblk1p1 does not exist.
Copy the wpa_supplicant.conf file from eMMC to /etc.
Unmount the eMMC.
umount: /mnt: not mounted.
Bringup the WiFi interface.
Successfully initialized wpa_supplicant
nl80211: kernel reports: Match already configured
nl80211: kernel reports: Match already configured
nl80211: kernel reports: Match already configured
nl80211: kernel reports: Match already configured
nl80211: kernel reports: Match already configured
nl80211: kernel reports: Match already configured
nl80211: kernel reports: Match already configured
nl80211: kernel reports: Match already configured
nl80211: kernel reports: Match already configured
nl80211: kernel reports: Match already configured
rfkill: Cannot open RFKILL control device
Fetch an IP address from the DHCP server.
udhcpc: started, v1.32.0
udhcpc: sending discover
udhcpc: sending discover
udhcpc: sending select for 192.168.1.37
udhcpc: lease of 192.168.1.37 obtained, lease time 43200
/etc/udhcpc.d/50default: Adding DNS 80.58.61.250
/etc/udhcpc.d/50default: Adding DNS 80.58.61.254
root@minized-sbc-base-2021-1:~#

Let's check the connection pinging element14.com

root@minized-sbc-base-2021-1:~# ping www.element14.com
PING www.element14.com (23.200.173.143): 56 data bytes
64 bytes from 23.200.173.143: seq=0 ttl=55 time=14.378 ms
64 bytes from 23.200.173.143: seq=1 ttl=55 time=18.164 ms
64 bytes from 23.200.173.143: seq=2 ttl=55 time=17.545 ms
64 bytes from 23.200.173.143: seq=3 ttl=55 time=46.294 ms
64 bytes from 23.200.173.143: seq=4 ttl=55 time=15.615 ms
64 bytes from 23.200.173.143: seq=5 ttl=55 time=15.537 ms
64 bytes from 23.200.173.143: seq=6 ttl=55 time=16.370 ms
64 bytes from 23.200.173.143: seq=7 ttl=55 time=16.192 ms
64 bytes from 23.200.173.143: seq=8 ttl=55 time=15.597 ms
64 bytes from 23.200.173.143: seq=9 ttl=55 time=16.156 ms
64 bytes from 23.200.173.143: seq=10 ttl=55 time=19.829 ms
64 bytes from 23.200.173.143: seq=11 ttl=55 time=16.309 ms
64 bytes from 23.200.173.143: seq=12 ttl=55 time=16.027 ms
64 bytes from 23.200.173.143: seq=13 ttl=55 time=55.066 ms
64 bytes from 23.200.173.143: seq=14 ttl=55 time=22.978 ms
64 bytes from 23.200.173.143: seq=15 ttl=55 time=16.908 ms
64 bytes from 23.200.173.143: seq=16 ttl=55 time=16.882 ms
64 bytes from 23.200.173.143: seq=17 ttl=55 time=18.089 ms
^C
--- www.element14.com ping statistics ---
18 packets transmitted, 18 packets received, 0% packet loss
round-trip min/avg/max = 14.378/20.774/55.066 ms
root@minized-sbc-base-2021-1:~# 

Checking packets transfer with iperf3. 

iperf is a tool for active measurements of the maximum achievable bandwidth on IP networks. It supports tuning of various parameters related to timing, protocols, and buffers. For each test it reports the measured throughput / bitrate, loss, and other parameters.

Output from the Minized Uart and Ubuntu console output face to face:

Checking the Webserver Demo

The Petalinux image that we have uploaded to Minized activates a demo websever application that runs on top of Python.

From the application we can interact with the LEDs on the board, both those of the Programmable Logic and those connected to the GPIOs of the Zynq ARM Processor System. 

We can also read the status of the user DIP Switch in the PL.

The image of the following web page is also served by the web server.

Like this PDF with the Avnet MiniZed development board brochure.

Build a New PetaLinux Image including our own App

We will:
• Create and install a custom application into the MiniZed’s PetaLinux file system.
• Compile a custom C application using a Makefile.
• Build MiniZed’s PetaLinux from scratch (given a BSP)
• Install the PetaLinux image onto the MiniZed

References

• MiniZed PetaLinux Technical Training 2021.1: Lesson 5
• MiniZed PetaLinux Technical Training 2021.1: Lesson 6

The new PetaLinux image will include a custom user application that will communicate via I2C with this HTU2X humidity and temperature sensor.

First we create a custom software application from our minized_sbc_base_2021_1 Petalinux Project folder

petalinux-create -t apps --template c --name te-sensor --enable

Then modify the recent created Bitbake Recipe te-sensor.bb adding the source files URIs and specifying the working directory

Then edit the makefile

And copy the application sources to meta-user/recipes-apps/te-sensor/file

Then build a new Petalinux Image

petalinux-config -c rootfs

As we have previously enabled the te-sensor app, it is already checked.

PetaLinux completes the configuration to get ready to build the kernel image.

ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/projects/minized_sbc_base_2021_1/project-spec/meta-user/recipes-apps/te-sensor$ petalinux-config -c rootfs
[INFO] Sourcing buildtools
[INFO] Silentconfig project
[INFO] Generating kconfig for Rootfs
[INFO] Menuconfig rootfs


*** End of the configuration.
*** Execute 'make' to start the build or try 'make help'.

[INFO] Generating plnxtool conf
[INFO] Successfully configured rootfs

Petalinux build

ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/projects/minized_sbc_base_2021_1/project-spec/meta-user/recipes-apps/te-sensor$ petalinux-build -c avnet-image-full
[INFO] Sourcing buildtools
[INFO] Building avnet-image-full
[INFO] Sourcing build environment
[INFO] Generating workspace directory
INFO: bitbake avnet-image-full
NOTE: Started PRServer with DBfile: /home/ealbertos/git/avnet/petalinux/projects/minized_sbc_base_2021_1/build/cache/prserv.sqlite3, IP: 127.0.0.1, PORT: 43175, PID: 23564
Loading cache: 100% |####################################################################################| Time: 0:00:01
Loaded 5139 entries from dependency cache.
Parsing recipes: 100% |##################################################################################| Time: 0:00:01
Parsing of 3509 .bb files complete (3503 cached, 6 parsed). 5144 targets, 269 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |###############################################################################| Time: 0:00:07
Checking sstate mirror object availability: 100% |#######################################################| Time: 0:00:15
Sstate summary: Wanted 243 Found 9 Missed 234 Current 1921 (3% match, 89% complete)
NOTE: Executing Tasks
NOTE: Tasks Summary: Attempted 6467 tasks of which 6392 didn't need to be rerun and all succeeded.
INFO: Successfully copied built images to tftp dir: /tftpboot
[INFO] Successfully built avnet-image-full
ealbertos@ealbertos-VirtualBox:~/git/avnet/petalinux/projects/minized_sbc_base_2021_1/project-spec/meta-user/recipes-apps/te-sensor$ 

Copy and mount rootfs to Minized

root@minized-sbc-base-2021-1:~# Starting tcf-agent: OK

PetaLinux 2021.1 minized-sbc-base-2021-1 ttyPS0


root@minized-sbc-base-2021-1:~# FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
Starting udev
udevd[102]: starting version 3.2.9
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
udevd[103]: starting eudev-3.2.9
zocl: loading out-of-tree module taints kernel.
input: ST LIS2DS Accelerometer Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input0
[drm] Probing for xlnx,zocl
zocl-drm amba_pl:zyxclmm_drm: IRQ index 32 not found
input: ST LIS2DS Step Counter Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input1
[drm] PR Isolation addr 0x0
[drm] Initialized zocl 0.0.0 -1061020 for amba_pl:zyxclmm_drm on minor 0
scsi 0:0:0:0: Direct-Access     Kingston DataTraveler 2.0 PMAP PQ: 0 ANSI: 0 CCS
input: ST LIS2DS Free Fall Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input2
sd 0:0:0:0: Attached scsi generic sg0 type 0
input: ST LIS2DS Tap Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input3
input: ST LIS2DS Double Tap Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input4
input: ST LIS2DS Step Detector Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input5
brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43430-sdio for chip BCM43430/1
input: ST LIS2DS Tilt Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input6
brcmfmac mmc1:0001:1: Direct firmware load for brcm/brcmfmac43430-sdio.xlnx,zynq-7000.txt failed with error -2
input: ST LIS2DS Significant Motion Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input7
input: ST LIS2DS Wake Up Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input8
input: ST LIS2DS Activity Sensor as /devices/soc0/amba_pl/41600000.i2c/i2c-1/1-001d/input/input9
brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43430-sdio for chip BCM43430/1
brcmfmac: brcmf_c_preinit_dcmds: Firmware: BCM43430/1 wl0: Feb  7 2018 06:14:09 version 7.45.98.45 (r683668 CY) FWID 01-56a4902c
lis2ds 1-001d: lis2ds: probed
sd 0:0:0:0: [sda] 8060928 512-byte logical blocks: (4.13 GB/3.84 GiB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] No Caching mode page found
sd 0:0:0:0: [sda] Assuming drive cache: write through
 sda: sda1
sd 0:0:0:0: [sda] Attached SCSI removable disk
EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
Starting tcf-agent: OK

PetaLinux 2021.1 minized-sbc-base-2021-1 ttyPS0


root@minized-sbc-base-2021-1:~#

Copy and convert the rootfs to emmc

dd if=/run/media/sda1/rootfs.wic of=/dev/mmcblk0

root@minized-sbc-base-2021-1:~# dd if=/run/media/sda1/rootfs.wic of=/dev/mmcblk0
5981988+0 records in
5981988+0 records out
3062777856 bytes (3.1 GB, 2.9 GiB) copied, 301.755 s, 10.1 MB/s
root@minized-sbc-base-2021-1:~#

Restoring MiniZed to the Factory State

As I have indicated, the Minized did not start well. Fortunately there is a tutorial to return the Minized to the initial factory state. So let's follow it.

 Restore QSPI and eMMC Factory Images

Programming the QSPI Flash Using XSCT

The file to be programmed into U2 can be found in the “Micron QSPI flash” sub-directory of the “Programming Files” directory of the zip archive that accompanies this document. Copy the file to be programmed, flash_only_boot_7007S.bin, to a directory, for example C:/tmp

As of XSCT 2017.2, the tools require that the FSBL (First-Stage Boot Loader) also be specified. For this, also copy the file zynq_fsbl.elf to the directory above (C:/tmp)

In the XSCT tool, at the xsct% prompt enter: cd /tmp

Then, to program the flash enter:

exec program_flash -f flash_only_boot_7007S.bin -fsbl zynq_fsbl.elf -flash_type qspi_single

****** Xilinx Software Commandline Tool (XSCT) v2022.2.0
  **** SW Build 0 on 2022-10-13-12:09:39
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.


xsct% cd /tmp
xsct% ls
WARNING: [Common 17-259] Unknown Tcl command 'ls' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
flash_fallback_7007S.bin  flash_only_boot_7007S.bin  zynq_fsbl.elf
xsct% exec program_flash -f flash_only_boot_7007S.bin -fsbl zynq_fsbl.elf -flash_type qspi_single

****** Xilinx Program Flash
****** Program Flash v2022.2 (64-bit)
  **** SW Build (by xbuild) on 2022-10-13-12:09:39
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:localhost:3121
Attempting to launch hw_server at TCP:localhost:3121

Connected to hw_server @ TCP:localhost:3121

Target not specified. Selecting target_id 2 (arm_dap) by default.

Retrieving Flash info...

Initialization done
Using default mini u-boot image file - C:/Xilinx/Vitis/2022.2/data\xicom\cfgmem\uboot\zynq_qspi_x4_single.bin
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x00113220 =====
READ: IO_PLL_CFG (0xF8000118) = 0x00113220
===== mrd->addr=0xF8000108, data=0x00024008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x00024008
Info:  Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B




U-Boot 2022.01-00146-g0526f91 (Jul 27 2022 - 03:07:47 -0600)



Model: Zynq CSE QSPI SINGLE Board

DRAM:  256 KiB

WARNING: Caches not enabled

Loading Environment from <NULL>... OK

In:    dcc

Out:   dcc

Err:   dcc

Zynq> sf probe 0 0 0


SF: Detected n25q128a13 with page size 256 Bytes, erase size 64 KiB, total 16 MiB

Zynq> Sector size = 65536.
f probe 0 0 0


Performing Erase Operation...
sf erase 0 FE0000


SF: 16646144 bytes @ 0x0 Erased: OK

Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 26 sec.
Performing Program Operation...
0%...sf write FFFC0000 0 10000

eMMC Initialization, reprogramming and Hardware tests

At the prompt, enter:

onetest.sh 

This should:

• format the eMMC
• copy files to eMMC from USB
• re-program the flash internally
• test the Wi-Fi and
• run a program that will test the I2C sensor while toggling the an LED
• after a key-press, shut down the system

43267036 bytes read in 14652 ms (2.8 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
   Using 'conf@1' configuration
   Trying 'kernel@0' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x100000d4
     Data Size:    3925272 Bytes = 3.7 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00008000
     Entry Point:  0x00008000
     Hash algo:    sha1
     Hash value:   f2ac69bcdcf755b54af38b5fd870f843fb0e9bc7
   Verifying Hash Integrity ... sha1+ OK
## Loading ramdisk from FIT Image at 10000000 ...
   Using 'conf@1' configuration
   Trying 'ramdisk@0' ramdisk subimage
     Description:  ramdisk
     Type:         RAMDisk Image
     Compression:  uncompressed
     Data Start:   0x103c28d8
     Data Size:    39323409 Bytes = 37.5 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: unavailable
     Entry Point:  unavailable
     Hash algo:    sha1
     Hash value:   d57b450521fd302afdc95bfe2e7c521b08745d10
   Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
   Using 'conf@1' configuration
   Trying 'fdt@0' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x103be6e0
     Data Size:    16712 Bytes = 16.3 KiB
     Architecture: ARM
     Hash algo:    sha1
     Hash value:   bd55217bdcb35db08dcfd467cfbbf0dd5e4cb754
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x103be6e0
   Loading Kernel Image ... OK
   Loading Ramdisk to 05a7f000, end 07fff711 ... OK
   Loading Device Tree to 05a77000, end 05a7e147 ... OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0x0
Linux version 4.9.0-xilinx-v2017.4 (sroussea@xterra1) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #1 SMP PREEMPT Thu Mar 22 22:22:16 MST 2018
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt:Machine model: xlnx,zynq-7000
bootconsole [earlycon0] enabled
cma: Reserved 16 MiB at 0x1f000000
Memory policy: Data cache writealloc
percpu: Embedded 14 pages/cpu @debc8000 s25932 r8192 d23220 u57344
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 130048
Kernel command line: console=ttyPS0,115200 earlyprintk
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 454596K/524288K available (6144K kernel code, 219K rwdata, 1504K rodata, 1024K init, 231K bss, 53308K reserved, 16384K cma-reserved, 0K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xe0800000 - 0xff800000   ( 496 MB)
    lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0700000   (7136 kB)
      .init : 0xc0900000 - 0xc0a00000   (1024 kB)
      .data : 0xc0a00000 - 0xc0a36fa0   ( 220 kB)
       .bss : 0xc0a36fa0 - 0xc0a70e08   ( 232 kB)
Preemptible hierarchical RCU implementation.
        Build-time adjustment of leaf fanout to 32.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
efuse mapped to e0800000
slcr mapped to e0802000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at e0802100
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at e080a000, irq=17
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
missing device node for CPU 1
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100058
CPU1: failed to boot: -1
Brought up 1 CPUs
SMP: Total of 1 processors activated (666.66 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xe0840000
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
e0000000.serial: ttyPS1 at MMIO 0xe0000000 (irq = 25, base_baud = 6249999) is a xuartps
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 26, base_baud = 6249999) is a xuartps
console [ttyPS0] enabled
console [ttyPS0] enabled
bootconsole [earlycon0] disabled
bootconsole [earlycon0] disabled
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41200000: registered, base is 1023
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41200000: dual channel registered, base is 1022
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41210000: registered, base is 1021
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41220000: registered, base is 1013
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
fpga-region fpga-full: FPGA Region probed
Advanced Linux Sound Architecture Driver Initialized.
Bluetooth: Core ver 2.22
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
Bluetooth: L2CAP socket layer initialized
Bluetooth: SCO socket layer initialized
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 4096 (order: 2, 16384 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...

Freeing initrd memory: 38404K (c5a7f000 - c8000000)
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
futex hash table entries: 512 (order: 3, 32768 bytes)
workingset: timestamp_bits=30 max_order=17 bucket_order=0
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
43c00000.serial: ttyS2 at MMIO 0x43c01000 (irq = 48, base_baud = 3000000) is a 16550A
xdevcfg f8007000.devcfg: ioremap 0xf8007000 to e081e000
[drm] Initialized
brd: module loaded
loop: module loaded
m25p80 spi0.0: found n25q128a13, expected m25p80
m25p80 spi0.0: n25q128a13 (16384 Kbytes)
4 ofpart partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000ff0000 : "boot"
0x000000270000-0x000000ff0000 : "kernel"
0x000000ff0000-0x000001000000 : "bootenv"
0x000001000000-0x000001000000 : "spare"
mtd: partition "spare" is out of reach -- disabled
libphy: Fixed MDIO Bus: probed
CAN device driver interface
e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
e0002000.usb supply vbus not found, using dummy regulator
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer at e088e000 with timeout 10s
Bluetooth: HCI UART driver ver 2.3
Bluetooth: HCI UART protocol H4 registered
Bluetooth: HCI UART protocol Broadcom registered
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
mmc0: queuing unknown CIS tuple 0x80 (2 bytes)
mmc0: queuing unknown CIS tuple 0x80 (3 bytes)
mmc0: queuing unknown CIS tuple 0x80 (3 bytes)
mmc0: queuing unknown CIS tuple 0x80 (7 bytes)
mmc0: queuing unknown CIS tuple 0x80 (3 bytes)
mmc0: queuing unknown CIS tuple 0x80 (6 bytes)
mmc1: SDHCI controller on e0101000.sdhci [e0101000.sdhci] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
NET: Registered protocol family 10
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20161123 t)
can: netlink gateway (rev 20130117) max_hops=1
Bluetooth: HIDP (Human Interface Emulation) ver 1.2
Bluetooth: HIDP socket layer initialized
Registering SWP/SWPB emulation handler
hctosys: unable to open rtc device (rtc0)
of_cfs_init
of_cfs_init: OK
ALSA device list:
  No soundcards found.
Freeing unused kernel memory: 1024K (c0900000 - c0a00000)
random: fast init done
mmc1: new high speed MMC card at address 0001
INIT: mmcblk1: mmc1:0001 Q2J55L 7.09 GiB
mmcblk1boot0: mmc1:0001 Q2J55L partition 1 16.0 MiB
version 2.88 bootingmmcblk1boot1: mmc1:0001 Q2J55L partition 2 16.0 MiB
mmcblk1rpmb: mmc1:0001 Q2J55L partition 3 4.00 MiB
 mmcblk1: p1
usb 1-1: new high-speed USB device number 2 using ci_hdrc

mmc0: new high speed SDIO card at address 0001
Starting udev
usb-storage 1-1:1.0: USB Mass Storage device detected
scsi host0: usb-storage 1-1:1.0
udevd[799]: starting version 3.2
udevd[800]: starting eudev-3.2
brcmutil: loading out-of-tree module taints kernel.
Loading modules backported from Linux version v4.12-0-g6f7da29
Backport generated by backports.git backports-20160324-111-g97b8d7c
usbcore: registered new interface driver brcmfmac
brcmfmac: brcmf_c_preinit_dcmds: Murata Customized Version: imx-morty-orga_r1.0;
brcmfmac: brcmf_c_preinit_dcmds: Firmware version = wl0: Oct 23 2017 03:55:53 version 7.45.98.38 (r674442 CY) FWID 01-e58d219f
brcmfmac: brcmf_c_preinit_dcmds: CLM version = API: 12.2 Data: 7.11.15 Compiler: 1.24.2 ClmImport: 1.24.1 Creation: 2014-05-26 10:53:55 Inc Data: 9.10.39 Inc Compiler: 1.29.4 Inc ClmImport: 1.36.3 Creation: 2017-10-23 03:47:14
scsi 0:0:0:0: Direct-Access     Kingston DataTraveler 2.0 PMAP PQ: 0 ANSI: 0 CCS
sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] 8060928 512-byte logical blocks: (4.13 GB/3.84 GiB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] No Caching mode page found
sd 0:0:0:0: [sda] Assuming drive cache: write through
 sda: sda1
sd 0:0:0:0: [sda] Attached SCSI removable disk
FAT-fs (mmcblk1p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
Populating dev cache
hwclock: can't open '/dev/misc/rtc': No such file or directory
Fri Mar 23 06:07:37 UTC 2018
hwclock: can't open '/dev/misc/rtc': No such file or directory
Starting internet superserver: inetd.
Running Minized Startup Script ...

Mounting /dev/mmcblk1p1 on /mnt/emmc

Mounting /dev/sda1 on /mnt/usb
MiniZed Startup Script DONE!
Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
 Removing any system startup links for run-postinsts ...
  /etc/rcS.d/S99run-postinsts
INIT: Entering runlevel: 5
Configuring network interfaces... ifconfig: SIOCGIFFLAGS: No such device
Starting system message bus: dbus.
Starting Dropbear SSH server: Generating key, this may take a while...
Public key portion is:
ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQCNz/67r7vSxJ356L3stq5eWXMDckaP/nhUFi5CzgOdF91N3Q9kR3Mj8oNLJNHvivj7K/kEmWjuM6vWxb9QgPi5VjDwWbIDnBea/sJoH6HGGheVvx3nbnFETjSZJAuh1j1VyGt4XL6v9JaYlc+tbYrqi0LD6DBJnXaTbmDHlkOzAzRrhzYgKQKK4ZHPNLn9lrDJMrHE/ecA2tYzrfwEwaPo6u/gPEToEVQq6J5dxkRjobMFsDd4EzlIVZg97T1aTM+dAOnY4OIa3dvzRVJXlZODnln+Cbz54MEaRd2NuUn4W0PL4UpbnFv5h+WQBkg/c2s8TOl2QVVdaMhTY+QeaKE1 root@MiniZed
Fingerprint: md5 c4:f9:d2:a4:9c:37:b6:03:27:4f:3d:13:dd:0b:f7:1f
dropbear.
Starting bluetooth
bluetoothd
/etc/init.d/rc: /etc/rc5.d/S20hostapd: /bin/sh^M: bad interpreter: No such file or directory
hwclock: can't open '/dev/misc/rtc': No such file or directory
Starting syslogd/klogd: done
Starting tcf-agent: OK

PetaLinux 2017.4 MiniZed /dev/ttyPS0

MiniZed login: root
Password:
root@MiniZed:~# onetest.sh
fdisk /dev/mmcblk1 (1 partition of 128MB)

The number of cylinders for this disk is set to 116224.
There is nothing wrong with that, but this is larger than 1024,
and could in certain setups cause problems with:
1) software that runs at boot time (e.g., old versions of LILO)
2) booting and partitioning software from other OSs
   (e.g., DOS FDISK, OS/2 FDISK)

Command (m for help): Selected partition 1

Command (m for help): Building a new DOS disklabel. Changes will remain in memory only,
until you decide to write them. After that the previous content
won't be recoverable.


The number of cylinders for this disk is set to 116224.
There is nothing wrong with that, but this is larger than 1024,
and could in certain setups cause problems with:
1) software that runs at boot time (e.g., old versions of LILO)
2) booting and partitioning software from other OSs
   (e.g., DOS FDISK, OS/2 FDISK)

Command (m for help): Command action
   e   extended
   p   primary partition (1-4)
Partition number (1-4): First cylinder (1-116224, default 1): Last cylinder or +size or +sizeM or +sizeK (1-116224, default 116224):
Command (m for help): The partition table has been altered.
Calling ioctl() to re-read partition table
fdisk: WARNING: rereading partition table failed, kernel still uses old table: Device or resource busy
sleep 1
mkdosfs -F 32 /dev/mmcblk1p1
sleep 1
/dev/mmcblk1p1 /mnt
ls -l /mnt
total 0
total 58396
drwxrwx---    2 root     disk          4096 Jul 16  2023 System Volume Information
-rwxrwx---    1 root     disk      43267036 Jul 16  2023 image.ub
-rwxrwx---    1 root     disk      16518116 Jul 16  2023 smallboot.bin
-rwxrwx---    1 root     disk           189 Jul 17  2023 wpa_supplicant.conf
cp /tempusb/image.ub /mnt/
cp /tempusb/wpa_supplicant.conf /mnt/
cp /tempusb/smallboot.bin /mnt/
ls -l /mnt
total 58385
-rwxrwx---    1 root     disk      43267036 Mar 23 06:08 image.ub
-rwxrwx---    1 root     disk      16518116 Mar 23 06:08 smallboot.bin
-rwxrwx---    1 root     disk           189 Mar 23 06:08 wpa_supplicant.conf
sync
cat /proc/mtd
dev:    size   erasesize  name
mtd0: 00ff0000 00001000 "boot"
mtd1: 00d80000 00001000 "kernel"
mtd2: 00010000 00001000 "bootenv"
mtd3random: crng init done
: 00000000 00000000 "spare"
flashcp smallboot.bin /dev/mtd0
umount /tempusb
umount /mnt
modprobe: module bcmdhd not found in modules.dep
Successfully initialized wpa_supplicant
rfkill: Cannot open RFKILL control device
IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
rfkill: Cannot get wiphy information
ifconfig: SIOCGIFFLAGS: No such device
udhcpc (v1.24.1) started
Sending discover...
IPv6: ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
Sending discover...
Sending select for 192.168.1.37...
Lease of 192.168.1.37 obtained, lease time 43200
/etc/udhcpc.d/50default: Adding DNS 80.58.61.250
/etc/udhcpc.d/50default: Adding DNS 80.58.61.254
sleep 1
/usr/bin/i2csensor
Examining the fields in all /sys/class/gpio/gpiochipN/label locations:
/sys/class/gpio/gpiochip1023/label = /amba_pl/gpio@41200000
/sys/class/gpio/gpiochip1013/label = /amba_pl/gpio@41220000
/sys/class/gpio/gpiochip1021/label = /amba_pl/gpio@41210000
/sys/class/gpio/gpiochip1022/label = /amba_pl/gpio@41200000
/sys/class/gpio/gpiochip895/label = zynq_gpio
Found the MIO[0] base = 895
Maximum AXI GPIO offset value = 1023
################################################################################
Testing the MiniZed GPIO and ST Micro LIS2DS12 I2C motion & temperature sensor
--------------------------------------------------------------------------------
The PS Button will reset the LED counter
The PL Switch selects the LED count or microphone output on the PL LED
################################################################################
With I2C device address 0x1d received WhoAmI = 0x43
CTL1 = 0x60 written
CTL4 = 0x01 written
gpio1021 set as in
gpio895 set as in
gpio947 set as out
gpio948 set as out
gpio1022 set as out
gpio1023 set as out
gpio1013 set as out
gpio1014 set as out
 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -251 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -257 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -252 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -251 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -247 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -259 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -248 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -262 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -256 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -256 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -243 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -245 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -260 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -241 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -263 OUT_T register = 0x11 -> Temperature = 42 degrees C.    Acceleration = X:  -260 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -264 OUT_T register = 0x10 -> Temperature = 41 degrees C.    Acceleration = X:  -245 OUT_T register = 0x11 -> Temperature = 42 degrees C.    Acceleration = X:  -264 OUT_T register = 0x11 -> Temperature = 42 degrees C.    Acceleration = X:  -253 OUT_T register = 0x11 -> Temperature = 42 degrees C.    Acceleration = X:  -262, Y:   +92, Z: +4147

*******************************************************************************************************
GPIO and I2C sensor test interrupted by the ENTER key.

shutdown -h now

Broadcast message from root@MiniZed (ttyPS0) (Fri Maà 23 06:12:06 2018):

INIT: Sending processes the TERM signal
root@MiniZed:~# Stopping Dropbear SSH server: stopped /usr/sbin/dropbear (pid 1460)
dropbear.
Stopping bluetooth
/usr/libexec/bluetooth/bluetoothd
Stopping system message bus: dbus.
/etc/init.d/rc: /etc/rc0.d/K20hostapd: /bin/sh^M: bad interpreter: No such file or directory
hwclock: can't open '/dev/misc/rtc': No such file or directory
Stopping syslogd/klogd: stopped syslogd (pid 1476)
stopped klogd (pid 1480)
done
Stopping tcf-agent: OK
Deconfiguring network interfaces... ifdown: interface eth0 not configured
done.
Sending all processes the TERM signal...
logout
Sending all processes the KILL signal...
Unmounting remote filesystems...
Deactivating swap...
Unmounting local filesystems...
reboot: System halted

Then reset again

U-Boot 2017.01 (Mar 22 2018 - 23:33:56 -0700)

Board: Xilinx Zynq
DRAM:  ECC disabled 512 MiB
MMC:   Card did not respond to voltage select!
sdhci@e0100000 - probe failed: -95
sdhci_transfer_data: Error detected in status(0x208000)!
Card did not respond to voltage select!

SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
U-BOOT for MiniZed

Hit any key to stop autoboot:  0
boot Petalinux
reading image.ub
43267036 bytes read in 14657 ms (2.8 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
   Using 'conf@1' configuration
   Trying 'kernel@0' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x100000d4
     Data Size:    3925272 Bytes = 3.7 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00008000
     Entry Point:  0x00008000
     Hash algo:    sha1
     Hash value:   f2ac69bcdcf755b54af38b5fd870f843fb0e9bc7
   Verifying Hash Integrity ... sha1+ OK
## Loading ramdisk from FIT Image at 10000000 ...
   Using 'conf@1' configuration
   Trying 'ramdisk@0' ramdisk subimage
     Description:  ramdisk
     Type:         RAMDisk Image
     Compression:  uncompressed
     Data Start:   0x103c28d8
     Data Size:    39323409 Bytes = 37.5 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: unavailable
     Entry Point:  unavailable
     Hash algo:    sha1
     Hash value:   d57b450521fd302afdc95bfe2e7c521b08745d10
   Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
   Using 'conf@1' configuration
   Trying 'fdt@0' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x103be6e0
     Data Size:    16712 Bytes = 16.3 KiB
     Architecture: ARM
     Hash algo:    sha1
     Hash value:   bd55217bdcb35db08dcfd467cfbbf0dd5e4cb754
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x103be6e0
   Loading Kernel Image ... OK
   Loading Ramdisk to 05a7f000, end 07fff711 ... OK
   Loading Device Tree to 05a77000, end 05a7e147 ... OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0x0
Linux version 4.9.0-xilinx-v2017.4 (sroussea@xterra1) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #1 SMP PREEMPT Thu Mar 22 22:22:16 MST 2018
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt:Machine model: xlnx,zynq-7000
bootconsole [earlycon0] enabled
cma: Reserved 16 MiB at 0x1f000000
Memory policy: Data cache writealloc
percpu: Embedded 14 pages/cpu @debc8000 s25932 r8192 d23220 u57344
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 130048
Kernel command line: console=ttyPS0,115200 earlyprintk
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 454596K/524288K available (6144K kernel code, 219K rwdata, 1504K rodata, 1024K init, 231K bss, 53308K reserved, 16384K cma-reserved, 0K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xe0800000 - 0xff800000   ( 496 MB)
    lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0700000   (7136 kB)
      .init : 0xc0900000 - 0xc0a00000   (1024 kB)
      .data : 0xc0a00000 - 0xc0a36fa0   ( 220 kB)
       .bss : 0xc0a36fa0 - 0xc0a70e08   ( 232 kB)
Preemptible hierarchical RCU implementation.
        Build-time adjustment of leaf fanout to 32.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
efuse mapped to e0800000
slcr mapped to e0802000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at e0802100
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at e080a000, irq=17
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
missing device node for CPU 1
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100058
CPU1: failed to boot: -1
Brought up 1 CPUs
SMP: Total of 1 processors activated (666.66 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xe0840000
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
e0000000.serial: ttyPS1 at MMIO 0xe0000000 (irq = 25, base_baud = 6249999) is a xuartps
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 26, base_baud = 6249999) is a xuartps
console [ttyPS0] enabled
console [ttyPS0] enabled
bootconsole [earlycon0] disabled
bootconsole [earlycon0] disabled
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41200000: registered, base is 1023
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41200000: dual channel registered, base is 1022
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41210000: registered, base is 1021
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41220000: registered, base is 1013
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
fpga-region fpga-full: FPGA Region probed
Advanced Linux Sound Architecture Driver Initialized.
Bluetooth: Core ver 2.22
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
Bluetooth: L2CAP socket layer initialized
Bluetooth: SCO socket layer initialized
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 4096 (order: 2, 16384 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...
Freeing initrd memory: 38404K (c5a7f000 - c8000000)
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
futex hash table entries: 512 (order: 3, 32768 bytes)
workingset: timestamp_bits=30 max_order=17 bucket_order=0
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
43c00000.serial: ttyS2 at MMIO 0x43c01000 (irq = 48, base_baud = 3000000) is a 16550A
xdevcfg f8007000.devcfg: ioremap 0xf8007000 to e081e000
[drm] Initialized
brd: module loaded
loop: module loaded
m25p80 spi0.0: found n25q128a13, expected m25p80
m25p80 spi0.0: n25q128a13 (16384 Kbytes)
4 ofpart partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000ff0000 : "boot"
0x000000270000-0x000000ff0000 : "kernel"
0x000000ff0000-0x000001000000 : "bootenv"
0x000001000000-0x000001000000 : "spare"
mtd: partition "spare" is out of reach -- disabled
libphy: Fixed MDIO Bus: probed
CAN device driver interface
e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
e0002000.usb supply vbus not found, using dummy regulator
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer at e088e000 with timeout 10s
Bluetooth: HCI UART driver ver 2.3
Bluetooth: HCI UART protocol H4 registered
Bluetooth: HCI UART protocol Broadcom registered
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
mmc0: queuing unknown CIS tuple 0x80 (2 bytes)
mmc0: queuing unknown CIS tuple 0x80 (3 bytes)
mmc0: queuing unknown CIS tuple 0x80 (3 bytes)
mmc0: queuing unknown CIS tuple 0x80 (7 bytes)
mmc0: queuing unknown CIS tuple 0x80 (3 bytes)
mmc0: queuing unknown CIS tuple 0x80 (6 bytes)
mmc1: SDHCI controller on e0101000.sdhci [e0101000.sdhci] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
NET: Registered protocol family 10
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20161123 t)
can: netlink gateway (rev 20130117) max_hops=1
Bluetooth: HIDP (Human Interface Emulation) ver 1.2
Bluetooth: HIDP socket layer initialized
Registering SWP/SWPB emulation handler
hctosys: unable to open rtc device (rtc0)
of_cfs_init
of_cfs_init: OK
ALSA device list:
  No soundcards found.
Freeing unused kernel memory: 1024K (c0900000 - c0a00000)
random: fast init done
mmc1: new high speed MMC card at address 0001
INIT: mmcblk1: mmc1:0001 Q2J55L 7.09 GiB
version 2.88 bootingmmcblk1boot0: mmc1:0001 Q2J55L partition 1 16.0 MiB
mmcblk1boot1: mmc1:0001 Q2J55L partition 2 16.0 MiB

mmcblk1rpmb: mmc1:0001 Q2J55L partition 3 4.00 MiB
 mmcblk1: p1
usb 1-1: new high-speed USB device number 2 using ci_hdrc
mmc0: new high speed SDIO card at address 0001
Starting udev
usb-storage 1-1:1.0: USB Mass Storage device detected
udevd[796]: starting version 3.2
scsi host0: usb-storage 1-1:1.0
udevd[798]: starting eudev-3.2
brcmutil: loading out-of-tree module taints kernel.
Loading modules backported from Linux version v4.12-0-g6f7da29
Backport generated by backports.git backports-20160324-111-g97b8d7c
usbcore: registered new interface driver brcmfmac
brcmfmac: brcmf_c_preinit_dcmds: Murata Customized Version: imx-morty-orga_r1.0;
brcmfmac: brcmf_c_preinit_dcmds: Firmware version = wl0: Oct 23 2017 03:55:53 version 7.45.98.38 (r674442 CY) FWID 01-e58d219f
brcmfmac: brcmf_c_preinit_dcmds: CLM version = API: 12.2 Data: 7.11.15 Compiler: 1.24.2 ClmImport: 1.24.1 Creation: 2014-05-26 10:53:55 Inc Data: 9.10.39 Inc Compiler: 1.29.4 Inc ClmImport: 1.36.3 Creation: 2017-10-23 03:47:14
scsi 0:0:0:0: Direct-Access     Kingston DataTraveler 2.0 PMAP PQ: 0 ANSI: 0 CCS
sd 0:0:0:0: [sda] 8060928 512-byte logical blocks: (4.13 GB/3.84 GiB)
sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] No Caching mode page found
sd 0:0:0:0: [sda] Assuming drive cache: write through
 sda: sda1
sd 0:0:0:0: [sda] Attached SCSI removable disk
FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
Populating dev cache
hwclock: can't open '/dev/misc/rtc': No such file or directory
Fri Mar 23 06:07:37 UTC 2018
hwclock: can't open '/dev/misc/rtc': No such file or directory
Starting internet superserver: inetd.
Running Minized Startup Script ...

Mounting /dev/mmcblk1p1 on /mnt/emmc

Mounting /dev/sda1 on /mnt/usb
MiniZed Startup Script DONE!
Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
 Removing any system startup links for run-postinsts ...
  /etc/rcS.d/S99run-postinsts
INIT: Entering runlevel: 5
Configuring network interfaces... ifconfig: SIOCGIFFLAGS: No such device
Starting system message bus: dbus.
Starting Dropbear SSH server: Generating key, this may take a while...
Public key portion is:
ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQDLnmdv2587YtOQDEuZnORo2aOWX4MG1ElApZc3uv0Ox7zUgd1MdCtbTkDM647JQB4fK2udLZFENnri0x3hSfm58o1nkPdUH1krrADCddRj+ygvtpJPROgf9SsGOA71//I5oAMnJfwU+9eJV4hsP0DGowVs4gqy28iKHJ7RLvoTnsuyB5lysDtDia7ZfqPurO7C8A2plgvWLFRwvukZoBkZ6q59X780M3P+8l4HZjw7oRjBMujkvrtoM4EHDw+ReLKUwV/DHfw0k4/BiMQkrSybMMtTWekj92wg19fv18+NBUpxmw/VEdNSUWvBxOfl9x0ZeDcql38VTY+X6zwqrWub root@MiniZed
Fingerprint: md5 eb:02:96:11:6a:8e:47:78:b4:dc:c2:e7:e8:93:58:4b
dropbear.
Starting bluetooth
bluetoothd
/etc/init.d/rc: /etc/rc5.d/S20hostapd: /bin/sh^M: bad interpreter: No such file or directory
hwclock: can't open '/dev/misc/rtc': No such file or directory
Starting syslogd/klogd: done
Starting tcf-agent: OK

PetaLinux 2017.4 MiniZed /dev/ttyPS0

MiniZed login:

Bluetooth testing

PetaLinux 2017.4 MiniZed /dev/ttyPS0

MiniZed login: root
Password:
root@MiniZed:~# bt.sh
Examining the fields in all /sys/class/gpio/gpiochipN/label locations:
/sys/class/gpio/gpiochip1023/label = /amba_pl/gpio@41200000
/sys/class/gpio/gpiochip1013/label = /amba_pl/gpio@41220000
/sys/class/gpio/gpiochip1021/label = /amba_pl/gpio@41210000
/sys/class/gpio/gpiochip1022/label = /amba_pl/gpio@41200000
/sys/class/gpio/gpiochip895/label = zynq_gpio
Found the MIO[0] base = 895
Maximum AXI GPIO offset value = 1023
Offsets written to /mnt/emmc/gpio_offsets.txt
Using MIO0_OFFSET from /mnt/emmc/gpio_offsets.txt : 895
EMIO0 : 949
bcm43xx_init
Set Controller UART speed to 3000000 bit/s
Flash firmware /etc/firmware/BCM43430A1.1DX.hcd
Set BDADDR UART: a0:cc:2b:ff:91:6f
Set Controller UART speed to 3000000 bit/s
Device setup complete
hci0:   Type: Primary  Bus: UART
        BD Address: A0:CC:2B:FF:91:6F  ACL MTU: 1021:8  SCO MTU: 64:1
        UP RUNNING PSCAN ISCAN
        RX bytes:1322 acl:0 sco:0 events:74 errors:0
        TX bytes:1236 acl:0 sco:0 commands:74 errors:0
        Features: 0xbf 0xfe 0xcf 0xfe 0xdb 0xff 0x7b 0x87
        Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3
        Link policy: RSWITCH SNIFF
        Link mode: SLAVE ACCEPT
        Name: 'BlueZ 5.41'
        Class: 0x200404
        Service Classes: Audio
        Device Class: Audio/Video, Device conforms to the Headset profile
        HCI Version: 4.0 (0x6)  Revision: 0x16
        LMP Version: 4.0 (0x6)  Subversion: 0x2209
        Manufacturer: Broadcom Corporation (15)

Scanning ...
        80:91:33:C6:21:54       n/a
        22:22:E7:19:AD:91       KM3
        DC:72:23:35:B4:49       Realtek Bluetooth
        D8:A3:5C:9A:DE:A5       [TV] WILMER
root@MiniZed:~#

Test the Dialog PMIC

The Dialog DA9062 Power-Management IC has an I2C interface that can be used to change the RTC (real-time clock) or to change the PMIC operating mode or even to adjust the pre-programmed voltage levels. Any adjustment of the power levels should of course be done with care, as changing these levels out of spec could damage components on MiniZed.

root@MiniZed:~# dialog-control
Examining the fields in all /sys/class/gpio/gpiochipN/label locations:
/sys/class/gpio/gpiochip1023/label = /amba_pl/gpio@41200000
/sys/class/gpio/gpiochip1013/label = /amba_pl/gpio@41220000
/sys/class/gpio/gpiochip1021/label = /amba_pl/gpio@41210000
/sys/class/gpio/gpiochip1022/label = /amba_pl/gpio@41200000
/sys/class/gpio/gpiochip895/label = zynq_gpio
Found the MIO[0] base = 895
Maximum AXI GPIO offset value = 1023
################################################################################
Ready to change the MiniZed Dialog DA9062 PMIC Buck Regulator mode
--------------------------------------------------------------------------------
The PS Button will reset the Dialog RTC time to midnight August 1st, 2017
The P key will change the mode to PWM  (0x80) for BUCK1, BUCK2 & BUCK3
The A key will change the mode to Auto (0xC0) for BUCK1, BUCK2 & BUCK3
Any other key to exit without change
################################################################################
gpio1021 set as in
gpio895 set as in
gpio947 set as out
gpio948 set as out
gpio1022 set as out
gpio1023 set as out
With I2C device address 0x58 and register address 0x9E Dialog BUCK1_CFG = 0xC0
With I2C device address 0x58 and register address 0x9D Dialog BUCK2_CFG = 0xC0
With I2C device address 0x58 and register address 0xA0 Dialog BUCK3_CFG = 0xC0
With I2C device address 0x58 Dialog date & time = 2000/01/01 00:20:08

******************************************************************************
Dialog control utility interrupted by the ENTER key.

The available test scripts are in the Linux /etc/local/bin/ folder. Useful scripts would be:

• format_emmc.sh - Formats the eMMC
• update_from_usb.sh - Copies files from the USB stick to the eMMC
• program_qspi_from_usb.sh - Internally program the QSPI flash with smallboot.bin
• wifi.sh - Makes the Wi-Fi connection
• bt.sh - Scans for Bluetooth devices
• i2c_test.sh - Reads the motion sensor and tests GPIO like LEDs

And with this I conclude my experiments during the training phase.

Updates on my training path

I have finished the review of all the topics of the three courses and I have done all the lab exercises. I already have the long-awaited three well-deserved badges. It has been a long road and I see that I still have many gaps in my training. I have to reinforce above all my knowledge of embedded Linux.

In the third blog of the series of training blogs,   P2P3 AMD Zynq-7000 SoC XADC. External Multiplexer Mode. ,  I introduced the design of a 16-in/2-out analog multiplexer that interfaced with the external multiplexer mode of the XADC of the MiniZed's AMD PSoC Zynq. I have already received this week the first version of the PCBs, we will see if I can use them for the final project of this challenge.

The modules are intended to connect to the Zynq's analog inputs but could also be used as digital multiplexers connected to the PMOD connectors.

Conclusion

This final part of the course is the most chaotic, as you have to work on the versions of the tools listed in the course, pushing yourself to experiment with other versions takes more time than I can spare. In any case, the adventure has been really interesting, I have even discovered that processes that I have been doing for years programming point of sale terminals are closely related to Yocto and I had not realized it because I was simply executing tools provided by the manufacturers. Something similar to what Petalinux does.

Path to Programmable III Training Blog Series

1. BLOG 1: P2P3 Getting Started. Clockless Hardware Blinky on the Avnet Minized 
2. BLOG 2:  P2P3 AMD Vitis portability and reuse. Migrating a Microblaze bare metal environmental monitor App to the Zynq architecture. 
3. BLOG 3:  P2P3 AMD Zynq-7000 SoC XADC. External Multiplexer Mode. 
4. BLOG 4:  P2P3 AMD Vivado Cascaded Integrator Comb (CIC) Compiler. PDM Microphone to PCM Decimation 
5. BLOG 5:  P2P3 Wireless sensors on the Avnet Minized. Getting Started with PetaLinux 
6. FINAL PROJECT:  AMD Zynq SoC MIDI Vintage Sound Synthesizer - Final