Table of Contents
- Audio Synth #1 - The project
- Audio Synth #2 - Board introduction and IDE setup
- Audio Synth #3 - Arduino to CmodS7 COMM Test
- Audio Synth #4 - Use PWM to control LED
- Audio Synth #5 - Testing the I2S PCM5102 DAC Decoder Board
- Audio Synth #6 - Sound generation with CmodS7
- Audio Synth #7 - Design challenge ends, project continues
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Revisiting the project’s objective
The stated objective of my project was the development of a test bench environment and a collection of Verilog modules that could be used to build such a synth. Since I was just beginning to learn Verilog (I still am!), I had no idea how expensive it is to implement such modules in an FPGA. My expectation was to find out that audio processing (e.g filters, various effects blocks) require much more resources than control & logic blocks, so I was very interested to find out if Cmod S7 is suitable for this specific audio application or if a more powerful board (in terms of FPGA, RAM memory, etc.) is needed.
About two weeks into the project I realised that due to my lack of experience with Verilog, I can not achieve the stated objective under the time constraints of this design challenge, so I switched to “learning mode” and tried to learn as much as I could (Verilog, Xilinx IP cores, etc..) in the time left by working on independent smaller projects that would focus of smaller parts of the original design.
Blog format
Being told on numerous occasions that I am a man of too few words, this time I tried to document as well as I could my work with the hope that this will be useful to a fellow engineer who, like me, has just started working with FPGAs. If my entries are too verbose, I apologise.
As my knowledge progressed, I resisted the temptation to go back and add new content or major corrections (other than fixing English grammar mistakes) to existing blogs. I decided instead to write Notes at the end of the blog. All changes are indicated in a Change Log section. To facilitate moving around the content, I also added a Table of Contents for each blog.
I hope the reader will find the links I provided in the text useful. For URLs, I prefer to use the whole URL rather than hiding it under one hyperlink-word. This way, it will be easier for the reader to find the information online, in case the links will change in the future.
Effort
I thought it would be interesting to provide an estimate of the time I spent on this project so far.
Even if I didn’t work as an embedded software engineer during the past few years, I consider I have a good experience in this area. I took a few classes in digital system design and DSP a long time ago, so I have some familiarity with digital circuitry. I started learning Verilog at the beginning of the challenge.
All together, during the past eight weeks, I have spent about fifteen hours per week for a total of about 120 hours (mostly on weekends except the last week when I worked for a few hours every night, btw. this week proved to be most productive of all).
Writing and publishing each blog took two to three hours, so I estimate the total time for documenting the work at around 20 hours.
I estimate the time spent with Vivado, writing Verilog code for design and simulation at around 40 hours. The rest of the time (about 60 hours) was spent learning Verilog, reading through data sheets and Xilinx docs, and browsing through Verilog books or code examples.
At the time of writing, I have a total of fourteen Verilog projects: about half of them are very simple projects I created in order to learn and experiment with Verilog and Vivado IDE. Out of these simple projects I included in the blogs the ones you can find in blogs #2, #3 and #4. The rest of the projects are a bit more complex (like the sound generation one in blog #6 or a project that generates a tone with a pitch that can be varied using a potentiometer which I just finished and I didn’t have the time to write about.)
Progress was very slow during the first half of the project with a very steep Verilog learning curve. At times, I found Vivado intimidating and felt lost trying to fix errors and warnings. On a couple of occasions I experienced significant difficulties with designs that worked fine in simulation but were not synthesizable and it took me some time to figure out how to find design blocks that can be synthesised in the FPGA. Things got better (a lot better actually) in the last week of the challenge, which proved to be the most productive one. The turning point was the sound generation project from blog #6 (440Hz pitch using square wave).
Here are a few words of wisdom from “Me at the end of the challenge” to “Me at the beginning”:
In retrospect, I would suggest choosing a smaller project, where the design is simple enough to allow the programmer to focus on implementation. In my case, the learning project I would propose now for this challenge (based on my accumulated experience) would be “A pitch generator using square waves of configurable frequency and duty cycle (CmodS7 and Arduino)”.
Without a reasonably good understanding of digital circuits, FPGA programming is not possible. Do not use a software design approach (data structure + algorithm) but try to think in terms of hardware (behaviour of hardware devices driven by clock signals).
Designs that work in simulation are not always synthesizable. You need to spend time to understand how Verilog blocks are implemented in hardware.
It is important to fix all errors and warnings in Vivado. If you leave unresolved warnings, make sure you know if that’s acceptable and what the implications are.
CmodS7 from Digilent
I found CmodS7 very easy to use. It does not have a lot of I/O devices (buttons, knobs, displays, video ports, etc…) but it has all that is needed for someone looking for a first FPGA board. I like the small form factor. I like that I can plug it in a breadboard and connect various other devices if needed. I also appreciate the 12 bit A/D converter from the Spartan 7 FPGA which I hope I can use in future projects. I think Digilent did a good job presenting the board: https://digilent.com/reference/programmable-logic/cmod-s7/start I found the info there very useful and from what I could see fairly accurate (with the exception of figure 6.1 from the Reference manual https://digilent.com/reference/programmable-logic/cmod-s7/reference-manual where the R,G,B diodes appear reversed, however in the schematic, the diodes are the way they should be!) At the beginning, I found Vivado difficult to use, but once I got to understand the design flow and spent time doing things in the IDE, it started to make sense. I was able to find a lot of information organised under Xilinx’s Design Hubs. I also found Xilinx’s user forum useful when fixing errors and warnings.
In conclusion, based on my experience, I would recommend this board to anyone who would like to start learning FPGA programming.
Design challenge ends, project continues
I will update the blog with scope samples once I find my old Hantek (currently hiding in one of the many boxes in storage!). If there is any interest, I will also add a few more Verilog projects to github after I clean the code a bit. I plan to continue this project in the second half of the year, when I hope to find the time to do it. Many thanks to Digilent and Element 14 for providing me with the opportunity to attend this design challenge!
