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On April 8th, 2020 at 11 AM CST // 4 PM GMT: Join us as to learn more about Using Overlays for Neural Networks with Bryan Fletcher and Fred Kellerman from Avnet:
Download Tech Sheets and the Slide Deck for this and the previous PYNQ webinar below!
Over the next few few months we've got some really exciting activities planned around PYNQ. PYNQ is an open source project started by Xilinx, which fuses the productivity of Python with the acceleration provided by programmable logic within the Zynq / Zynq MPSoC. The tight coupling of processing system (PS) and programmable logic (PL) in the Zynq / Zynq MPSoC allows for the creation of systems that are more responsive, deterministic, and power efficient when compared to traditional CPU or GPU-based applications. This increase in performance is due to the ability to leverage the parallel nature of the programmable logic to move accelerate the application from the sequential software world to the parallel world enabled by programmable logic.
Until recently, a programmable logic solution required advanced digital design skills which limited its accessibility to software developers. If you're new to PYNQ then I would suggest checking out this excellent webinar On Demand:
Bryan Fletcher will be joined by Fred Kellerman to answer all your Ultra96-V2 and PYNQ questions. Bryan has contributed many posts regarding the Ultra96-V2 to the community which you can read about here:
- Introducing Ultra96-V2
- LPDDR4 Memory differences between Ultra96-V1 and Ultra96-V2
- Zynq UltraScale+ PMU and the Ultra96-V2 On/Off Controller
- Industrial Temperature Ultra96-V2 Single Board Computer
- Ultra96-V2 Clocking Architecture
Visit the Ultra96-V2 community where you can find Technical Specifications, Reference Designs, and Technical Documents.
Like Ultra96, the Ultra96-V2 is an Arm-based, Xilinx Zynq UltraScale+ 
MPSoC development board based on the Linaro 96Boards Consumer Edition (CE) specification. Ultra96-V2 is available in more countries around the world as it has been designed with a certified radio module from Microchip. Engineers have options of connecting to Ultra96-V2 through a Webserver using integrated wireless access point capability or to use the provided PetaLinux desktop environment which can be viewed on the integrated Mini DisplayPort video output. Multiple application examples and on-board development options are provided as examples. Ultra96-V2 provides four user-controllable LEDs. Engineers may also interact with the board through the 96Boards-compatible low-speed and high-speed expansion connectors by adding peripheral accessories such as those included in the MikroE Click Mezzanine for 96Boards (available as an accessory). Micron LPDDR4 memory provides 2 GB of RAM in a 512M x 32 configuration. Wireless options include 802.11b/g/n Wi-Fi and Bluetooth 5 Low Energy. The radio module is Agency Certified in over 75 countries. UARTs are accessible on a header as well as through the expansion connector. JTAG is available through a header. The convenient JTAG/UART Pod (available as an accessory) provides both JTAG and UART connections via USB. I2C is available through the expansion connector. Two Microchip USB3320 USB 2.0 ULPI Transceivers and one Microchip USB5744 4-Port SS/HS USB Controller Hub enable multiple USB connections. Ultra96-V2 provides one upstream (device) and two downstream (host) USB 3.0 connections. A USB 2.0 downstream (host) interface is provided via the high-speed expansion. An IDT VersaClock 6E clock generator provides timing for USB 3.0, USB 2.0, DisplayPort, and the Xilinx MPSoC primary clock input. The integrated Infineon programmable power regulators generate all on-board voltages from an external 12V supply (available as an accessory) as well as providing access to power telemetry through PMBus connectivity.
 | ultra96-V2 Datasheet.pdf |
 | Ultra96-V2 Product Brief.pdf |
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 | Ultra96-V2 Rev1.00 C-grade BOM.pdf |
 | Ultra96-V2 Rev1.02 I-grade BOM.pdf |
 | Ultra96-V2 Rev1.04 C-grade BOM.pdf |
 | Ultra96-V2-GSG-v1_1.pdf |
 | Ultra96-V2-Rev1-BOM.pdf |
 | PYNQ_Webinar_8May19.pdf |
 | Using Python Overlays to Experiment with Neural Networks v1.pdf |
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