Hercules LaunchPad and GaN FETs - Part 2: Make a BoosterPack

A PCB! And it's a Boosterpack (whatever that is)!

I don't know what you intend for the tracking (please don't say it's going to be a job for an autorouter, entertaining though that might be), but wouldn't it work better if you rotated P3 (the output connector) by 180 degrees. It would then allow you to have the power ground (input gnd - GaN - output gnd) as copper on the top layer. Since all the power tracking could then be copper on the top, you might consider whether it would work well enough as a 2-layer board.

I'm using the layout advice in  the 'Layout Considerations for LMG5200 GaN Power Stage' appnote from the manufacturer.

They have a proposal for a double layer pcb in the datasheet with this remark:

To maximize the efficiency benefits of fast switching, its extremely important to optimize the board layout such

that the power loop impedance is minimum. When using a multilayer board (more than 2 layers), power loop

parasitic impedance is minimized by having the return path to the input capacitor (between VIN and PGND) small

and directly underneath the first layer

 

[...]

 

Two-layer boards are not recommended for use with LMG5200 device due to the larger power loop inductance.

However, if design considerations allow only two board layers, place the input decoupling capacitors immediately

behind the device on the back-side of the board to minimize loop inductance.

Four layer layout:

Two layer layout:

Your board visualisations look nice.

Took me a few moments there to work out the different views and figure out how the top related to the bottom - the bottom capacitors sit directly under the top capacitors, don't they.

What are the internal planes like? Are they both ground (split between power ground and signal ground, maybe)? It would be useful to show them, so we can see how they relate to the top and bottom.

A great thing about what you are doing (for me, at least) is that it raises a lot of questions that I really don't know the answers to. A layout to deal with rise times of a nS or two at high currents is complicated electrically in ways you don't even need to consider at lower frequencies [we all seem to be gradually turning into rf engineers]. It does make me feel a bit tentative about making any suggestions about the layout - where I say things here, take them as issues for discussion rather than advice.

In a comment above I said that vias look horrible at high frequency. Having glibly stated that, I'm now trying to work out how true it actually is [currently rereading 'High-Speed Signal Propagation' by Johnson and Graham].

This next bit is very much 'thinking aloud'; it's not meant as a lecture.

The reason I asked about the ground planes was because the capacitance that exists between the top trace carrying the Vin power and the power ground, although fairly small (*see below), will be supplying power to the GAN chip much quicker than the physical capacitors that we can see on the board (the physical capacitors are held back by their lead inductance which limits the rate at which the current can ramp up). That would suggest that fattening up the Vin copper would be of advantage (thereby increasing the capacitance). Widening it also reduces the inductance further, which again helps matters.

* if I've got my calculation right, 1sq cm with 0.3mm spacing would be something like 30pF (with FR4 as a dielectric). It's not much and won't power things for long, but the value lies in it being almost pure capacitor and next to no inductance so it gets off to a flying start.

I'm much less clear in my thinking about the capacitors on the input and whether the arrangement is a good one. The starting point is that paralleling effectively reduces lead inductance. It doesn't really - each component still has the same lead inductances - but the group looks better than a single component would in its place. Put ten capacitors in parallel and it's like we had a single part with a tenth of the lead inductance. So no problem there.

I'm less clear about whether having different sizes of capacitor is good or not - you could imagine a wave effect where the small parts with the lowest inductance start things off and then the larger parts come in in turn. But textbooks tell you not to mix capacitors [that are close in value] because of resonance effects - with different self-resonant frequencies you end up in a messy situation with the capacitors interacting with each other.

The other area I'm thinking about is the vias. They seem to be complicated to model because we're looking at rf effects that depend on geometry and the inductance has to be considered as part of a loop [you can't just say that a particular via is equivalent to a particular inductance and treat it as though it were a lumped component]. About the only thing I'm reasonably sure of is that multiple vias are essential - you must stitch with groups of vias to get the inductance down to an acceptable value. But even there things aren't quite clearcut because vias that are very close together interact [the magnetic field around one via couples to adjacent ones].

Anyway, I'll carry on reading and if my head doesn't explode perhaps I'll have some answers in a few days.

Loads of things to reply to . I'll start with one: the planes capacity:

this is a hybrid FET driver, with virtually everything that's time/capacity/inductance critical embedded inside the IC package. There are two exceptions:

- the separate high and low input signals: you need to keep the traces approx. the same lenght - else you can't achieve deadband as short as 7ns.

- the inductance of that return path at the switching output we discussed in the comments. That's the only high current high frequency part that's exposed to the pcb. The other side of the coil, the ac component of the signal is already significantly reduced.

the rest of the layout is more focused in being able to get significant current in and out, and to get heat dissipated. At that point, any board capacity is almost an added value to the real capacitors.

... i thought I had published a blog about the pcb layout, but I see it's still in my drafts - unfinished.

I'll upload the KiCAD project to that post, so that you can see what net is connected to wich plane.

I've posted a blog about the PCB layout. The idea was to include my own layout to that blog, but I can't upload images since this afternoon.

It does contain the 4 layers of the TI evaluation kit - captures of their published Gerber files.

Hercules LaunchPad and GaN FETs - Part 3a: BoosterPack Layout - Reference Design

I finally have the post with the PCB design up, I'm still struggling with e14 image uploads - the schematic couldn' be updated to the post.

But at least I have the 4 layers, with annotations to what flood fill holds what signal.

Hercules LaunchPad and GaN FETs - Part 3b: BoosterPack Layout - my version

I finally have the post with the PCB design up, I'm still struggling with e14 image uploads - the schematic couldn' be updated to the post.

But at least I have the 4 layers, with annotations to what flood fill holds what signal.

Hercules LaunchPad and GaN FETs - Part 3b: BoosterPack Layout - my version

Hi Jan,

This is looking very nice!!

Thanks. Loads of work, these all-floodfill PCBs.

Details about the custom PCB footprints and schematic symbols:

Hercules LaunchPad and GaN FETs - Side Note A: BoosterPack Layout - Custom KiCad Parts