Interface custom VHDL code with PS simple_register

Hi

You need to make new ports in your user_logic and simple_register HDL files and then Rescan User Repositories and make these ports external in XPS.  Then go back into PlanAhead and edit the top level HDL to include the connections you need.  There's a useful tutorial here in the "Hardware Development Lab":

http://www.xilinx.com/training/embedded/embedded-design-tutorials.zip

Matthew

Thanks for the link Matthew.
So I gather that just connecting a VHDL block to the simple_register is not the right way to proceed. ALso, how about the clock? I was under the impression that if I instantiated simple_register with 16 internal registers slv_reg0-slv_reg15, I would be able to read and write from all the 16 registers using the SDK interface (even when these ports are connected to my custom VHDL block).

Hi again

Yes, the interface with the registers in user_logic.vhd is exactly the same no matter what is connected to the ports in simple_register.  You can connect the clock directly from the FCLK_CLK0 (or another clock if you want) by creating another external port for it.

Connecting a VHDL block is fine, but as far as I'm aware you need to make the ports external in XPS and connect them in PlanAhead to do that.  Whenever you generate the top level VHDL you need to add your component to it and connect the ports which were made external in XPS to the ports in your component.

Matthew

First of all, thanks a lot for the link to the tutorials. It was interesting to go through the tutorials and implement the GPIO register as a peripheral on the PS.

So I followed the same example and started with a basic zynq PS. Then I instantiated a simple_register mentioned in ZynqGeek's blog post. I instantiated 8 of those registers in the PS ports section. Now when I generate the VHDL instantiation template I don't see any ports to connect to the VHDL logic.

What I understand from your second post is that in my top VHDL module (in PlanAhead),
1. I instantiate the PS with it's set of ports (no mention of simple_register),
2. Instantiate the simple_register.vhd block and modify it to take the register value out?
3. Connect the register port to my VHDL block.
4. Synthesize and implement?

Thanks!

When you generate the VHDL template there should be ports which you have made external in XPS.  In the hardware tutorial at 2-4 they make the GPIO_LED_8bits external so it will now appear in the instantiation template.

The simple_register is in the same position as the GPIO IP connected to the interconnect and your VHDL entity should be connected in the same way their debouncer.vhd file is.  (The files for the tutorial are located in the support directory in case you hadn't already found them)

It might be possible to connect the entity as you were trying to in your original post, but you would need to edit the .pao files for your custom peripheral.  I think the way they do it is much easier to follow.

So in summary:
1. In XPS, Create your custom peripheral using the wizard
2. Create the ports to connect that peripheral to your VHDL entity
3. Rescan User Repositories and connect the ports as external
4. In PlanAhead, Generate the top level VHDL (it should have ports for your peripheral because you made them external)
5. Instantiate your VHDL entity as a component in the top level and connect it to the ports
6. Sythesize, Implement, Generate Bitstream

Hope that clears things up, if you need a further look at connecting additional ports to user_logic.vhd Chapter 9 of UG873 gives an example for a counter connected to the LEDs, but most of the steps are referenced from Chapter 6 of the EDK CTT after the in-depth look at the wizard.  Links Below:

UG873
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/ug873-zynq-ctt.pdf

EDK CTT
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/edk_ctt.pdf

Matthew

Matthew: Thanks for all the hints.
Couple of things I learned:
1. I changed user_logic.vhd to bring two external ports. However, I had a lot of XST errors because I was not able to take the values correctly from slv_reg0 signal. I realized that just scanning the user repositories is not enough. I did a "Add new peripheral" and then imported the .vhd files and the .pao file to have the ports scanned again.
2. I did spend a lot of time understanding how to have values propagated from the Bus2IP_Data signal and the IP2Bus_Data signals. It's sometimes very confusing.
3. I added all the ports synthesized, implemented my design and now I am stuck with SDK error. I followed the instructions in the tutorial to set up a project with an empty application and when I try to build my project, I see an error with "include xbasic_types.h" I haven't been able to resolve this yet.

ANy suggestions?

Thanks again!

Hi

If re-scanning the user repositories isn't enough you may have to edit the .mpd file in the 'Data' folder.  I think that is covered in at least one of those documents.  The AXI-Lite interface is not the most intuitive, but it's a lot easier to deal with than the full specification and it is robust.

What error message are you getting from xbasic_types.h?  It is possible that you don't need it so you could try commenting it out.

Matthew

Hi FPGAgeek,

what kind of error do you see in SDK? I get an error too, because it seems that "xbasic_types.h" is an unknown file and for this reason "Xuint32" is an undefined data type. I commented the #include and defined Xuint32 as "typedef unsigned long Xuint32;" ad it's all right!!

I'm trying to connect a simple adder.vhd to our simple_register.vhd but I'm facing some problems. What I've done:

1) added some custom ports in user_logic to perform handshaking with the adder;
2) modified simple_register instantiating adder.vhd and connecting it to user_logic;
3) re-imported the modified peripheral in XPS and performed a "Design Rule Checked": no errors.
4) back to PlanAhead to generate BitStream. During synthesis I get errors and I'm not able to solve them, as I can't understand what's happened..

My question is: Did I make some mistakes?
Note: I'm not intereted in adding external ports in simple_register. I just want to write data, make a sum and read the result..

Thanks in advance

Now it is sometime since I worked with SDK, so please forgive me for vague guidance. Most likely in your SDK project properties you forgot to set the checkbox that links your project and the BSP or there is missing path to BSP include files.

Thank you darpla for your answer. Unfortunately I'm not able to reach SDK development. I'm stuck in PlanAhead 'cause an error occurs while generating bitstream.
Any suggestions?

sticken