Parallella $99 board now open hardware on Github

Although Adapteva are still fulfilling their Kickstarter committment, their shop is already open for preorders of the 16-core Epiphany board for November delivery.  Three options appear to be available:

If "No GPIO" means none, zero, zilch, that doesn't appear very enticing, I must say.  If this describes the situation accurately, the range of application of the basic board will be a lot narrower than expected.  And if the Zynq-7020-based Parallella-16 costs $199, then the price of the Parallella-64 is probably going to be very unfriendly.

Morgaine Dinova wrote:

 

If "No GPIO" means none, zero, zilch, that doesn't appear very enticing, I must say.  If this describes the situation accurately, the range of application of the basic board will be a lot narrower than expected.  And if the Zynq-7020-based Parallella-16 costs $199, then the price of the Parallella-64 is probably going to be very unfriendly.

Given there's an 'optional upgrade' for the GPIO connectors it seems likely that the difference is simply down to installing the connectors.  Any volunteers to hand solder four of those ?

In some ways you can see the reasoning, not having them will not prevent you doing software things on the Epiphany processor.  If you really want gpio, and don't care so much about the Epiphany there are probably better boards.

Am I correct in thinking that the only difference between the 7010 and 7020 is more FPGA space ?  If so, what's this board really meant to be, a dev board for parallel processing on the Epiphany, or an FPGA dev board ?

From your general experience of Xilinx, could the Zynq's FPGA be used to create an effective DRAM controller for notebook-type DRAM residing on a daughter card?  The kernel has NUMA functionality so it should be possible to tell it that certain regions of memory are slower than the 1GB on the Parallella main board.  (I'll have to check that it would be cached properly by the processor though, otherwise performance would be dreadful.)

OTOH if that would be a lot  slower than the main SDRAM then I suppose one could kill two birds with one stone by making the first daughter card a SATA controller, and then just use swap space to provide more usable memory for processes.  That's well known for producing highly unsatisfactory performance though.

(I'm still kicking around ideas for how to turn Parallella into the heart of a general purpose computer.  Unlike most ARM boards with their non-expandable on-board RAM, the Zynq does at least in principle  allow such memory expansion.)

Morgaine Dinova wrote:

 

From your general experience of Xilinx, could the Zynq's FPGA be used to create an effective DRAM controller for notebook-type DRAM residing on a daughter card?  The kernel has NUMA functionality so it should be possible to tell it that certain regions of memory are slower than the 1GB on the Parallella main board.  (I'll have to check that it would be cached properly by the processor though, otherwise performance would be dreadful.)

 

OTOH if that would be a lot  slower than the main SDRAM then I suppose one could kill two birds with one stone by making the first daughter card a SATA controller, and then just use swap space to provide more usable memory for processes.  That's well known for producing highly unsatisfactory performance though.

 

(I'm still kicking around ideas for how to turn Parallella into the heart of a general purpose computer.  Unlike most ARM boards with their non-expandable on-board RAM, the Zynq does at least in principle  allow such memory expansion.)

Without doing much research, here's my SWAG:  The Zynq has a single DDR3/DDR2/LPDDR2 controller that supports a 16- or 32-bit data bus.  This is going to make it hard to use 64-bit wide DIMMs.  I have limited knowledge of the details of DDR, but my understanding is that the signal levels and timing are nasty and you're much better off using a dedicated controller that knows how to optimize the timing.  LPDDR2 might be a lot simpler.

For performance, I would think you're pretty much stuck with the single Zynq DDR controller.  You could certainly do a slower SDR controller in logic, but finding SDR DIMMs of a reasonable size could be problematic in the 21st Century.

John Beetem wrote:

 

For performance, I would think you're pretty much stuck with the single Zynq DDR controller.

I assume you mean the one that's already driving the on-board 1GB of SDRAM, right?  So, we can't use that.

You could certainly do a slower SDR controller in logic, but finding SDR DIMMs of a reasonable size could be problematic in the 21st Century.

Well the requirement, phrased in the least demanding way, is simply to have something not too far from the CPU that behaves like real R/W memory and doesn't have the dreadful performance characteristics of on-disk swap space.  So while a controller implemented in FPGA won't give us memory timings as optimized as the main-board dedicated memory interface, it won't really matter too much as long as it's not orders of magnitude slower.  (It will matter if it's not cacheable, but that's a separate fight.)

I don't actually know the form factor details of Parallella daughter cards, but as long as one axis is open to allow a bit of physical extension, there shouldn't be anything stopping laptop SODIMMs from being used, or even full-length DIMMs, so there's no shortage of commodity-priced memory around.

I just found Xilinx's "7 Series FPGAs Memory Interface Solutions v2.0 User Guide" ... all 623 pages ot it.  It seems to apply to the Artix-7 series FPGA architecture as used in the Zynq 7010 and 7020, so I expect the answers I need are in there somewhere, give or take some Zynq-specific restrictions.  This isn't going to be easy to figure out.

Like John I haven't researched this thoroughly but I can suggest the following Lattice parts (for a parallel processor experiment). They do offer DDR3 support for up to 72 bit wide memory and specifically refer to DIMMs. The IP needed is often sold for $99 although the official price is higher - I've never used it.

Lattice ECP3  - LFE-17-EA-7LFN484C £32

Lattice ECP3 = LFE-95-EA-7LFN484C £191

1 off prices from Mouser (and remember Lattice ECP3 are the cheapo guys in this field)

Both these chips are in 484 pin BGA so no fun to solder.

Every now and then Lattice offer dev boards for $99

If you can settle for  a much lower performance the Lattice XP2 FPGAs will support DDR2 but I think you'll still need to go for BGA to get enough pins.

On the other hand if you can live with SDRAM at lowish speeds (100MHz any width you like) I'll give you my IP for the controller.

The best experimental hand soldered platform I can suggest would be XP2-17 in 208 pin TQFP with 2 x 100MHz SDRAMs for 32 bit wide access - really very limited compared with what you can do if you go BGA.

I have a plan to attempt BGA soldering with less than £100 worth of gear but I'm not going to try a £200 chip to start with. Cheaper suggestions in 1mm pitch are welcome.

MK

That's extremely interesting, Michael.  One question that immediately popped into mind though is whether the tradeoffs that encourage extreme density in commercial designs are actually appropriate in OSHW.

Why go for very high density packages with all the problems of soldering BGAs and then requiring expensive boards with a lot of layers to route out all those pins, when less dense packages are easier to fit and less expensive for community production?  Dense FPGAs commonly command premium prices too, so a couple of small ones could be a lot cheaper, as well as easier to route using fewer layers because you can spread them out.

Clearly I'm generalizing a bit too much, but isn't there something to be said for the less dense route in OSHW?

Morgaine Dinova wrote:

 

One question that immediately popped into mind though is whether the tradeoffs that encourage extreme density in commercial designs are actually appropriate in OSHW.

I'd agree that it's not, at least not for the kind of OSHW you're supposed to be able to assemble yourself with little more than a soldering iron.

The problem comes back to that commercial aspect we were discussing previously.  The manufacturers of the devices are under no obligation to produce things that are easy for OSHW to use. If their major market is happy with BGA, then why would they bother with QFP ?  As Michael suggests, pin count becomes a problem sooner or later and high pin count QFP style devices have their own problems anyway.

However, the downside for OSHW is that if you're not prepared to deal with parts that have the density seen in commercial designs then you're likely to be artifically limiting your creativity, especially as newer parts start to become available only in BGA.  Of course the other side is that you may be limited anyway by not being able to afford to get a BGA design produced for you by a commercial outfit when you're only talking tiny numbers.

Does the net effect mean that OSHW becomes self limiting simply due to needing to take the step into commercial production, but not wanting to do that ?

Michael Kellett wrote:

On the other hand if you can live with SDRAM at lowish speeds (100MHz any width you like) I'll give you my IP for the controller.

The tradeoffs start to become interesting. DDR3 is cheap because it's the current mass market choice, but needs expensive BGA based FPGA. Older memory, DDR, SDRAM, tend to be smaller and many times more expensive, but allow a cheaper FPGA. Save on one hand, lose on the other.  All depends on the design requirements I suppose, but I don't see it being clear cut at all.

I was interested to see one of the videos on the BBB where Jason Kridner stated that the savings moving from DDR2 on the original beaglebone to DDR3 on the black was the thing that made adding eMMC & HDMI along with getting the end cost much closer to RPi possible.

Michael Kellett wrote:

 

I have a plan to attempt BGA soldering with less than £100 worth of gear but I'm not going to try a £200 chip to start with.  Cheaper suggestions in 1mm pitch are welcome.

 

MK

Xilinx Spartan-3A in FT(G)256 1mm 16x16 BGA.  One nice thing about FPGA is that you can use JTAG boundary scan to verify connectivity for testing your process.

selsinork wrote:

 

However, the downside for OSHW is that if you're not prepared to deal with parts that have the density seen in commercial designs then you're likely to be artifically limiting your creativity, especially as newer parts start to become available only in BGA.  Of course the other side is that you may be limited anyway by not being able to afford to get a BGA design produced for you by a commercial outfit when you're only talking tiny numbers.

 

Does the net effect mean that OSHW becomes self limiting simply due to needing to take the step into commercial production, but not wanting to do that ?

I think it means that you're limited to what you can get in the form of a plug-in module, something Morgaine talked about recently.  If the interest in FPGAs becomes solid enough, it's easy enough for SparkFun and/or AdaFruit to make modules for them, particularly since a single PCB can usually handle several pin-compatible devices.  But the volume has to be there.

selsinork wrote:

 

However, the downside for OSHW is that if you're not prepared to deal with parts that have the density seen in commercial designs then you're likely to be artifically limiting your creativity, especially as newer parts start to become available only in BGA.  Of course the other side is that you may be limited anyway by not being able to afford to get a BGA design produced for you by a commercial outfit when you're only talking tiny numbers.

 

Does the net effect mean that OSHW becomes self limiting simply due to needing to take the step into commercial production, but not wanting to do that ?

I think it means that you're limited to what you can get in the form of a plug-in module, something Morgaine talked about recently.  If the interest in FPGAs becomes solid enough, it's easy enough for SparkFun and/or AdaFruit to make modules for them, particularly since a single PCB can usually handle several pin-compatible devices.  But the volume has to be there.

John Beetem wrote:

 

I think it means that you're limited to what you can get in the form of a plug-in module, something Morgaine talked about recently.  If the interest in FPGAs becomes solid enough, it's easy enough for SparkFun and/or AdaFruit to make modules for them, particularly since a single PCB can usually handle several pin-compatible devices.  But the volume has to be there.

OSHW-friendly companies like Sparkfun and Adafruit can help us out by making breakout boards for tiny SMD packages that many OSHW people find difficult to handle, and that includes pre-mounting BGAs.  To me that suggests that even if there will be no home-solderable devices in the future, it won't mean the end of home construction.  I don't see a future of doom and gloom in that area --- quite the opposite in fact, as the maker and OSHW scene is blooming, and  small companies like the above are often happy to exploit small niches of demand.  I'm sure that many others will join them.

On the separate issue of equipment form-factors, although commercial manufacturing and marketing seems obsessed with miniaturizing everything, OSHW communities don't necessarily have the same needs and can be resistent to the marketing message that "tiny == cool" when they also know that "tiny == unmaintainable".

As environmental awareness rises, unmaintainable devices are seen more and more as products of an extremely blind waste economy, an inherently destructive aspect of current-day electronics and extremely dangerous to our own future.  There's a perfect storm gathering in power as waste tips turn into mountains and leeching toxins pollute our water supplies, and unless we do something about the forces that are feeding it, there are bad times ahead for the world.  It goes far beyond OSHW's normal interests, but perhaps it's time to change that.  Creating modular and highly maintainable computers would be a small step in the right direction.

Certainly there is some scope for break out boards but they don't really answer for the high performance chips. FPGAs with 484 or more pins are common and the bigger processors have far more pins than that. A breakout board ends up with an awful lot of pins but with high speed signals you can't use simple 0.1" or 2 mm headers but you have to use expensive impedance controlled connectors.

The only way round this is to put more on the board so it morphs from breakout board to SBC with pcie/ethernet/usb but of course that is exactly what we don't want.

My way forward on this is to try and assemble more exciting parts using simple "kitchen" type technology.

MK

Michael Kellett wrote:

 

My way forward on this is to try and assemble more exciting parts using simple "kitchen" type technology.

I agree, and I'd also like to add another small point about effective engineering to reduce the dependency on complex top-end devices.

Systems almost never have an equally high-speed requirement in all their parts.  In the huge majority of cases, only a few small sections have a need for an FPGA's top speed, and the rest of a solution performs more leisurely duties.  What this means is that if you slap a microcontroller alongside an FPGA, in most cases you'll get exactly the same level of performance determined by the high-speed logic, yet you'll be able to use a much smaller FPGA because the slower parts of the solution are handled in software.  That's much more effective engineering.

And once you observe that more effective engineering means splitting off designs into sections, only a few of which need to be high-speed, then you can get away from the high-cost parts containing a billion gates and needing out-of-reach assembly techniques.  "Kitchen" type technology then becomes adequately effective.  OSHW doesn't need ultra-dense devices with all the problems they introduce.  They're a poor fit for us.