Parallella $99 board now open hardware on Github

Although Adapteva are still fulfilling their Kickstarter committment, their shop is already open for preorders of the 16-core Epiphany board for November delivery.  Three options appear to be available:

If "No GPIO" means none, zero, zilch, that doesn't appear very enticing, I must say.  If this describes the situation accurately, the range of application of the basic board will be a lot narrower than expected.  And if the Zynq-7020-based Parallella-16 costs $199, then the price of the Parallella-64 is probably going to be very unfriendly.

Morgaine Dinova wrote:

 

If "No GPIO" means none, zero, zilch, that doesn't appear very enticing, I must say.  If this describes the situation accurately, the range of application of the basic board will be a lot narrower than expected.  And if the Zynq-7020-based Parallella-16 costs $199, then the price of the Parallella-64 is probably going to be very unfriendly.

Given there's an 'optional upgrade' for the GPIO connectors it seems likely that the difference is simply down to installing the connectors.  Any volunteers to hand solder four of those ?

In some ways you can see the reasoning, not having them will not prevent you doing software things on the Epiphany processor.  If you really want gpio, and don't care so much about the Epiphany there are probably better boards.

Am I correct in thinking that the only difference between the 7010 and 7020 is more FPGA space ?  If so, what's this board really meant to be, a dev board for parallel processing on the Epiphany, or an FPGA dev board ?

John Beetem wrote:

 

Xilinx prices on Spartan chips are very attractive IMO.

The words "reasonable" (used earlier) and "attractive" as you've been using them are different to the way in which I prefer to use them.  What they mean to you appears to be "Less costly than I expected them to be", or perhaps "Less costly than they were before".  It has no bearing on their actual cost relative to the state of technology.

If people have gotten used to the latest iLust gadget costing $500, then with the above semantic a price drop to $300 would probably be described as making them "reasonable" or "attractive", despite the fact that it's still bloody extortionate when similar functionality is available for under $100.  Of course there's room for quibbling over quality, but in the case of digital semiconductors that excuse practically evaporates because digital technology without the required noise margins simply doesn't work.

I accept that Spartans can be purchased for not much more than the price of packaging, 3A's all the way down to single digit unit prices, but my comment was really aimed at Zynq, or should have been.

My argument about Zynq pricing would have been stronger if I could point to a native Chinese ARM+FPGA with similar functionality but a much lower price tag, but alas I can't, and I'm not even sure how to  start looking.  (And the documentation might not be in any language I understand anyway.)  Despite this weakness, my gut feeling is that Xilinx is making no effort to bring this family of devices to the mass market (which is entirely a function of price), despite having had ample time to do so since the concept was sprung on the world ages ago.  I think it likes to give this particular product an air of exclusivity (and charge accordingly), which is why it's so hard to find the device listed, priced and in stock.

Parallella seems to be very much an oddball, a product that democratizes Zynq despite Xilinx's best efforts at keeping it away from the unwashed masses.

Morgaine Dinova wrote:

 

John Beetem wrote:

 

Xilinx prices on Spartan chips are very attractive IMO.

 

The words "reasonable" (used earlier) and "attractive" as you've been using them are different to the way in which I prefer to use them.  What they mean to you appears to be "Less costly than I expected them to be", or perhaps "Less costly than they were before".  It has no bearing on their actual cost relative to the state of technology.

 

If people have gotten used to the latest iLust gadget costing $500, then with the above semantic a price drop to $300 would probably be described as making them "reasonable" or "attractive", despite the fact that it's still bloody extortionate when similar functionality is available for under $100.  Of course there's room for quibbling over quality, but in the case of digital semiconductors that excuse practically evaporates because digital technology without the required noise margins simply doesn't work.

 

I accept that Spartans can be purchased for not much more than the price of packaging, 3A's all the way down to single digit unit prices, but my comment was really aimed at Zynq, or should have been...

Well, the first marketing materials for Zynq said "starting at $15" [Xcell Journal 2Q2011] and maybe they'll get down there some day.  As far as comparing to iGewgaws, it's a question of volume.  A technology that sells 10M - 100M/year is going to be a lot cheaper than FPGAs, which rarely get into high-volume devices for the simple reason that if you're going to have high volumes you're better off synthesizing your Verilog/VHDL into a real ASIC.  FPGA proponents talk about "getting an FPGA into a cell phone", but the reality is that the margins aren't there and cell phones don't need the logic flexibility an FPGA offers.  Proponents say "but wait!  the FPGA is reconfigurable!" but IMO it's hard enough to get one design to work in an FPGA, much less a whole slew of them.  This would change if they'd open up the bitstream formats.

I'd be quite happy to get that $15 chip   Maybe someday.  It takes a long time for Xilinx parts to get cheaper, and usually you don't see much price movement on generation N until generation N+1 comes out.  Most of the stuff I read about Xilinx these days is about 3-D chip construction and other ways to make their chips more expensive.  Well, that's probably where they make their money, and Spartan is there because otherwise a competitor would take over the entry level, and then leverage themselves up.  As long as the Chinese stay away from FPGAs, I don't expect much change, and FPGAs haven't reached enough volume to get the Chinese interested.

Back to Zynq pricing, I guess I'm not sticker-shocked because my then-company looked into Virtex II-Pro a long time ago.  Our products were mostly based on PowerPC, so the idea of having PowerPC integrated with an FPGA seemed pretty good.  Then we saw the price tag, and quickly went with a cheap PowerPC SoC and a cheap  Spartan-IIE, interconnected with PCI.

Where FPGAs really stand out IMO is medium-volume applications where designing an ASIC is too expensive and too risky, but the design is not practical without a custom chip.  If it's a communication product where protocols may be evolving (or you need to add others in the future), the flexibility of an SRAM-based FPGA is an excellent match, since you can ship a new release of the hardware with each software release.  FPGA are also great for communication test equipment, where the protocols needed to be tested evolve and you'd like to minimize the effort of updating your equipment.  But it's a medium volume product, though with enough margin that current FPGA pricing is, well, pretty "attractive".

John Beetem wrote:

 

But it's a medium volume product, though with enough margin that current FPGA pricing is, well, pretty "attractive".

Grrrrrr ....

I wonder why in these discussions so many people overlook Lattice. Easily the most fun FPGA company and they DO have FPGAs in phones. Their Ultra Low Density approach fits well with John's definition of sophisticated and is currently delivering a million parts per day at very low (single $ or less) prices.

(MInor rant over -BTW I have no connection with Lattice other than as a customer).

Even though I don't use any Xilinx parts at the moment I think the cost/pricing issue is more complex than just the cost of the silicon. Xilinx (and I assume Altera) spend more on software development than on hardware development. They also spend huge sums on research which makes the mega parts possible. They have to get that back somehow and whilst both companies make a profit I don't think they do much better overall than, for example, Linear Technolgy and nothing like as well as Intel have done. (That's in term sof margins not size).

And much as I like Lattice their approach with simple cheap bits hasn't made them as big as X or A.

I think we'll see the FPGA market grow a lot more - the potential for cheap tiny parts is huge - but tiny is more about price and package - the capability is getting better all the time. I'm already able to get 1000 LUTs for £2 in 100s off but, I think, <<£1 for 100k. The next generation (Lattice 'X03) will expand tiny to cover 640 to 22k LUTs and at lower prices. The space for ASICs gets smaller with each advance of FPGAs - I don't play in the meg chip zone but there is a lot of scope with the cheapo parts.

Hmmm - this has got very off topic - sorry.

MK

I agree with Michael there, and I'd much rather see open source support the underdog than the field leader --- it's easier to gain some influence that way, among other things, and the immoveable leader then feels the lack of love and sometimes reacts.  Look at nVidia as an example of that, against all expectations actually sitting up and taking notice when it got the finger of disrepute pointed at it.

Lattice MachXO2 looks nice, and 'XO3 will probably be even nicer, especially when spelled with an 'O'.

Michael Kellett wrote:

 

Hmmm - this has got very off topic - sorry.

Readers would get extremely confused if we ever managed to stay on topic.

Michael Kellett wrote:

 

I wonder why in these discussions so many people overlook Lattice. Easily the most fun FPGA company and they DO have FPGAs in phones. Their Ultra Low Density approach fits well with John's definition of sophisticated and is currently delivering a million parts per day at very low (single $ or less) prices.

(MInor rant over -BTW I have no connection with Lattice other than as a customer).

I need to take closer look at Lattice when I've cleared some of my higher priorities.  My general position is that until Brand L opens its architecture there isn't a compelling reason to switch from Brand X or Brand A, but I'm curious to play with iCE40 and MachXO2/3.

Xilinx (and I assume Altera) spend more on software development than on hardware development.

We all know there's a simple solution to that problem, one that Intel and other processor manufacturers figured out a long time ago   IMO semiconductor companies should do what they do well, and let FLOSS do its magic for the rest of the problem.

I earlier gazed into the future and handwaved:

 

"Lattice MachXO2 looks nice, and 'XO3 will probably be even nicer"

Well then I got around to looking at their MachXO3 page and discovered ...

Lattice writes:

 

Integrated Support for the Latest Interfaces - Simplify and optimize your system design using MIPI, PCIe, and GbE hard blocks.

OK, now they really have my attention!   This is a gigabit IoT device on a chip at CPLD prices.

Due "October" ...

Morgaine Dinova wrote:

Michael Kellett wrote:

 

Hmmm - this has got very off topic - sorry.

Readers would get extremely confused if we ever managed to stay on topic.

tts the off topic stuff that makes the messages (threads) so interessting.

Walt

Morgaine Dinova wrote:

 

I earlier gazed into the future and handwaved:

 

"Lattice MachXO2 looks nice, and 'XO3 will probably be even nicer"

 

Well then I got around to looking at their MachXO3 page and discovered ...

 

Lattice writes:

 

Integrated Support for the Latest Interfaces - Simplify and optimize your system design using MIPI, PCIe, and GbE hard blocks.

OK, now they really have my attention!   This is a gigabit IoT device on a chip at CPLD prices.

 

Due "October" ...

I'll save my opinion until I find out what's the cheapest MachXO3 that has PCIe and/or GbE.  For example, you can't get Zynq PCIe until you get up to to the Z-7030, or Spartan-6 PCIe until you get to the XC6SLX25T.

Michael Kellett wrote:

 

Hmmm - this has got very off topic - sorry.

Not off-topic IMO.  At US$99 Parallella is the cheapest Zynq board out there, so it's perfectly reasonable to discuss alternative FPGA boards.  And what is an FPGA if not a very-fine-grain highly-interconnected parallel processor array, nicht wahr?

Michael Kellett wrote:

 

Hmmm - this has got very off topic - sorry.

Not off-topic IMO.  At US$99 Parallella is the cheapest Zynq board out there, so it's perfectly reasonable to discuss alternative FPGA boards.  And what is an FPGA if not a very-fine-grain highly-interconnected parallel processor array, nicht wahr?

John Beetem wrote:

 

And what is an FPGA if not a very-fine-grain highly-interconnected parallel processor array, nicht wahr?

That's an interesting way of looking at it.  And it immediately made me think of a "just for fun" project:

1. Define an extremely basic soft processor core, eg. 4 registers, input/output, and some arithmetic ops.
2. Replicate them as a 2D array for a typical FPGA, linking in/out channels N/S/E/W as in Epiphany.
3. Profit.  (This step optional.)

That could be a lot of fun.  Anyone care to guess the gatecount per minimalist soft processor?

There are loads of real soft processor cores out there, but  I've not seen one intended for processor arrays.  And as you point out, FPGAs are inherently highly parallel, so using the gates up to define powerful sequential CPUs seems backwards.  Very simple soft cores in large numbers would retain the parallelism.

PS. This could even be on topic, if implemented in the Parallella's Zynq.  It might need the bigger 7020 though, as there could be little room left in the 7010.

From your general experience of Xilinx, could the Zynq's FPGA be used to create an effective DRAM controller for notebook-type DRAM residing on a daughter card?  The kernel has NUMA functionality so it should be possible to tell it that certain regions of memory are slower than the 1GB on the Parallella main board.  (I'll have to check that it would be cached properly by the processor though, otherwise performance would be dreadful.)

OTOH if that would be a lot  slower than the main SDRAM then I suppose one could kill two birds with one stone by making the first daughter card a SATA controller, and then just use swap space to provide more usable memory for processes.  That's well known for producing highly unsatisfactory performance though.

(I'm still kicking around ideas for how to turn Parallella into the heart of a general purpose computer.  Unlike most ARM boards with their non-expandable on-board RAM, the Zynq does at least in principle  allow such memory expansion.)

Morgaine Dinova wrote:

 

From your general experience of Xilinx, could the Zynq's FPGA be used to create an effective DRAM controller for notebook-type DRAM residing on a daughter card?  The kernel has NUMA functionality so it should be possible to tell it that certain regions of memory are slower than the 1GB on the Parallella main board.  (I'll have to check that it would be cached properly by the processor though, otherwise performance would be dreadful.)

 

OTOH if that would be a lot  slower than the main SDRAM then I suppose one could kill two birds with one stone by making the first daughter card a SATA controller, and then just use swap space to provide more usable memory for processes.  That's well known for producing highly unsatisfactory performance though.

 

(I'm still kicking around ideas for how to turn Parallella into the heart of a general purpose computer.  Unlike most ARM boards with their non-expandable on-board RAM, the Zynq does at least in principle  allow such memory expansion.)

Without doing much research, here's my SWAG:  The Zynq has a single DDR3/DDR2/LPDDR2 controller that supports a 16- or 32-bit data bus.  This is going to make it hard to use 64-bit wide DIMMs.  I have limited knowledge of the details of DDR, but my understanding is that the signal levels and timing are nasty and you're much better off using a dedicated controller that knows how to optimize the timing.  LPDDR2 might be a lot simpler.

For performance, I would think you're pretty much stuck with the single Zynq DDR controller.  You could certainly do a slower SDR controller in logic, but finding SDR DIMMs of a reasonable size could be problematic in the 21st Century.

John Beetem wrote:

 

For performance, I would think you're pretty much stuck with the single Zynq DDR controller.

I assume you mean the one that's already driving the on-board 1GB of SDRAM, right?  So, we can't use that.

You could certainly do a slower SDR controller in logic, but finding SDR DIMMs of a reasonable size could be problematic in the 21st Century.

Well the requirement, phrased in the least demanding way, is simply to have something not too far from the CPU that behaves like real R/W memory and doesn't have the dreadful performance characteristics of on-disk swap space.  So while a controller implemented in FPGA won't give us memory timings as optimized as the main-board dedicated memory interface, it won't really matter too much as long as it's not orders of magnitude slower.  (It will matter if it's not cacheable, but that's a separate fight.)

I don't actually know the form factor details of Parallella daughter cards, but as long as one axis is open to allow a bit of physical extension, there shouldn't be anything stopping laptop SODIMMs from being used, or even full-length DIMMs, so there's no shortage of commodity-priced memory around.

I just found Xilinx's "7 Series FPGAs Memory Interface Solutions v2.0 User Guide" ... all 623 pages ot it.  It seems to apply to the Artix-7 series FPGA architecture as used in the Zynq 7010 and 7020, so I expect the answers I need are in there somewhere, give or take some Zynq-specific restrictions.  This isn't going to be easy to figure out.

Like John I haven't researched this thoroughly but I can suggest the following Lattice parts (for a parallel processor experiment). They do offer DDR3 support for up to 72 bit wide memory and specifically refer to DIMMs. The IP needed is often sold for $99 although the official price is higher - I've never used it.

Lattice ECP3  - LFE-17-EA-7LFN484C £32

Lattice ECP3 = LFE-95-EA-7LFN484C £191

1 off prices from Mouser (and remember Lattice ECP3 are the cheapo guys in this field)

Both these chips are in 484 pin BGA so no fun to solder.

Every now and then Lattice offer dev boards for $99

If you can settle for  a much lower performance the Lattice XP2 FPGAs will support DDR2 but I think you'll still need to go for BGA to get enough pins.

On the other hand if you can live with SDRAM at lowish speeds (100MHz any width you like) I'll give you my IP for the controller.

The best experimental hand soldered platform I can suggest would be XP2-17 in 208 pin TQFP with 2 x 100MHz SDRAMs for 32 bit wide access - really very limited compared with what you can do if you go BGA.

I have a plan to attempt BGA soldering with less than £100 worth of gear but I'm not going to try a £200 chip to start with. Cheaper suggestions in 1mm pitch are welcome.

MK

That's extremely interesting, Michael.  One question that immediately popped into mind though is whether the tradeoffs that encourage extreme density in commercial designs are actually appropriate in OSHW.

Why go for very high density packages with all the problems of soldering BGAs and then requiring expensive boards with a lot of layers to route out all those pins, when less dense packages are easier to fit and less expensive for community production?  Dense FPGAs commonly command premium prices too, so a couple of small ones could be a lot cheaper, as well as easier to route using fewer layers because you can spread them out.

Clearly I'm generalizing a bit too much, but isn't there something to be said for the less dense route in OSHW?

Morgaine Dinova wrote:

 

One question that immediately popped into mind though is whether the tradeoffs that encourage extreme density in commercial designs are actually appropriate in OSHW.

I'd agree that it's not, at least not for the kind of OSHW you're supposed to be able to assemble yourself with little more than a soldering iron.

The problem comes back to that commercial aspect we were discussing previously.  The manufacturers of the devices are under no obligation to produce things that are easy for OSHW to use. If their major market is happy with BGA, then why would they bother with QFP ?  As Michael suggests, pin count becomes a problem sooner or later and high pin count QFP style devices have their own problems anyway.

However, the downside for OSHW is that if you're not prepared to deal with parts that have the density seen in commercial designs then you're likely to be artifically limiting your creativity, especially as newer parts start to become available only in BGA.  Of course the other side is that you may be limited anyway by not being able to afford to get a BGA design produced for you by a commercial outfit when you're only talking tiny numbers.

Does the net effect mean that OSHW becomes self limiting simply due to needing to take the step into commercial production, but not wanting to do that ?

Michael Kellett wrote:

On the other hand if you can live with SDRAM at lowish speeds (100MHz any width you like) I'll give you my IP for the controller.

The tradeoffs start to become interesting. DDR3 is cheap because it's the current mass market choice, but needs expensive BGA based FPGA. Older memory, DDR, SDRAM, tend to be smaller and many times more expensive, but allow a cheaper FPGA. Save on one hand, lose on the other.  All depends on the design requirements I suppose, but I don't see it being clear cut at all.

I was interested to see one of the videos on the BBB where Jason Kridner stated that the savings moving from DDR2 on the original beaglebone to DDR3 on the black was the thing that made adding eMMC & HDMI along with getting the end cost much closer to RPi possible.

Michael Kellett wrote:

 

I have a plan to attempt BGA soldering with less than £100 worth of gear but I'm not going to try a £200 chip to start with.  Cheaper suggestions in 1mm pitch are welcome.

 

MK

Xilinx Spartan-3A in FT(G)256 1mm 16x16 BGA.  One nice thing about FPGA is that you can use JTAG boundary scan to verify connectivity for testing your process.