5V UARTs on SBCs?

CP2103 fits except for the encapsulated...

Powered from USB, and taking VCC from the board (arduino, RPi, BBB...) to connect it to the VCCIO of the CP2103

Hi gihu!

Very nice part. I should add it to the list here, it looks closely related to the CP2102 (I think the main difference is the EPROM on the 2103 vs the PROM on the 2102, but I need to read the datasheet more thoroughly).

Unfortunately as you say, the package is the thing that doesn't fit. The through-hole requirement is quite limiting. I also want to avoid having the extra wire if possible, not too sure yet until I try it out.

With a 3.3V logic out it is ok for 3.3V and 5V UARTS (perhaps not some older SBCs if the 5V levels are not compatible : ( but hoping to just heavily restrict current to try to make it safe for 1.8V UARTs too (no idea yet if this is practical, need to do some sums), also making it safe for both boards if RX/TX are accidentally swapped. The receive side just needs to be tolerant, which is easier to accommodate.

It is only for development purposes, not production, so I don't overly mind if it doesn't work at high bitrates or with all historical boards. This way I can stick to through-hole parts entirely I think, and have something that doesn't need thinking before connecting. And maybe a proto area, so people can customize or add their own functionality (since there is I2C and ADC capability on the MCP2221), or the RS232 capability that Doug suggests, since that would be handy too. Example documented adaptations for RS232, MIDI etc would be cool.

This is the kind of thing I'm envisioning (replace the text 5V with 3.3V, and the text 3.3V with 1.8V). I was just trawling the Internet to see if I could find any supporting docs to determine if it isn't totally insane.. This is from a Microchip doc (PDF).

It might be an over-assumption that the diodes will be present. I can test it with some example 1.8V UART SBCs to see what the trend is in I/O pad design on ICs (because usually the UART will also be configurable as an I/O pin on application processors I think). If it works, then we'll have a USB-serial that needs no thought when plugging into 5V, 3.3V or 1.8V boards.

EDIT: Also considering the opto-isolation part, combined with the above. Together there would be the best of both worlds. It would be really nice to have it opto-isolated from the PC.

It's not "totally insane", it just falls in that grey area between hacking and good design.

Reverse biassed diodes are a very common way to protect the input/output from ESD [electro-static discharge] but they aren't the only way so you are maybe taking a bit of a gamble (though probably not much of one). I don't know very much about IC design, but as I understand it the metal-contact diodes are essentially free because they use the metalisation layers that distribute the power and don't require extra processing steps. They're also nice because they are fast, but also have low capacitance and hardly affect the signals when they're not operating. So I think the manufacturers would need good reasons not to use them, which would only apply to more specialised chips where they might want to operate very fast, or have very low input leakage, or whatever. Or, of course, in a situation where an input is designed to tolerate more than the supply voltage.

Manufacturers are [understandably] nervous of you operating outside the rails because the CMOS process can latch up. If you raise the input above the rail, you get what is effectively a 4-layer structure like an SCR that will latch on until the power is removed. If what's driving the input can supply enough current then it will permanently damage the chip. Again, I'm a bit hazy about this, but I think it might be a diode drop above, so the Schottky protection diode will come in before the latch-up occurs and save the day, but only if the current is modest. It's also complicated because the IC is a circuit and, as with any other circuit, there's no such thing as a perfect ground or supply rail, so with only a couple of hundred millivolts in hand it doesn't take much in the way of ground bounce or noise spikes on the supply to compromise that. 

If you're prepared to use the target supply and some transistors there are various ways to do the level translation (so you don't have to use one of these new-fangled IC thingummibobs). Most obvious is a pair of transistors as switches, giving a double inversion. Another possibility, which I thought I'd try simulating, is an emitter follower like this:

The schematic is drawn in TI's Spice simulator. [Just happens to be what I'm using at the moment. LT also provide a perfectly good simulation tool; I'm not making a case for one or the other, or indeed any other Spice simulation tool.] The voltage generator is a 5V square wave at 1MHz with 25nS edges. The 10 ohm resistor is my (very crude) model of the output FETs in the UART. C1 represents the parasitic capacitance of the input pin on the receiver, the PCB track and a (very minimal - couple of centimetres) piece of wire for the connection. Transient simulation looks like this:

That's equivalent to 2 MBits/s, so would be fine for 115200. I was looking at it that fast because I got sidetracked into examining the effect of the speed-up capacitor (C2) and how much value it adds [whether it might be a marginal improvement or a significant one].

This is the simulation with C2 removed, so it does have a significant effect at higher speeds, but probably isn't necessary at 115200:

Where the circuit falls down (other than needing a supply from the target, which you were trying to avoid) is in the poor drive of the output capacitance. Even with just 40pF the output waveform is unbalanced. With 400pF [an additional couple of meters of cable] we get this, which would be useless at 2 Mbaud, though it might work for 115200.

If you're prepared to use the target supply and some transistors there are various ways to do the level translation (so you don't have to use one of these new-fangled IC thingummibobs). Most obvious is a pair of transistors as switches, giving a double inversion. Another possibility, which I thought I'd try simulating, is an emitter follower like this:

The schematic is drawn in TI's Spice simulator. [Just happens to be what I'm using at the moment. LT also provide a perfectly good simulation tool; I'm not making a case for one or the other, or indeed any other Spice simulation tool.] The voltage generator is a 5V square wave at 1MHz with 25nS edges. The 10 ohm resistor is my (very crude) model of the output FETs in the UART. C1 represents the parasitic capacitance of the input pin on the receiver, the PCB track and a (very minimal - couple of centimetres) piece of wire for the connection. Transient simulation looks like this:

That's equivalent to 2 MBits/s, so would be fine for 115200. I was looking at it that fast because I got sidetracked into examining the effect of the speed-up capacitor (C2) and how much value it adds [whether it might be a marginal improvement or a significant one].

This is the simulation with C2 removed, so it does have a significant effect at higher speeds, but probably isn't necessary at 115200:

Where the circuit falls down (other than needing a supply from the target, which you were trying to avoid) is in the poor drive of the output capacitance. Even with just 40pF the output waveform is unbalanced. With 400pF [an additional couple of meters of cable] we get this, which would be useless at 2 Mbaud, though it might work for 115200.

Hi Jon,

I think it's a good idea to use BJTs in this design, easy to find in through-hole of course, and cheap.

Definitely the Rx side will, to implement the voltage tolerance to allow interop for 1.8V logic through to 5V logic.

The latch-up is a concern, as you say maybe it is an over-assumption that the I/O pads will always have the diodes present.

But I am trying to do everything possible to avoid having the extra wire, or switches.. I may give up though if it seems too risky -

but willing to sacrifice a test Odroid if that's what it takes! : (

I just don't have many 1.8V SBCs here to experiment with.

I wonder if I combine the current limiting and use something similar to what you've simulated to provide a (say) 2.3V logic level, then

I'll avoid latch-up at 1.8V for any devices which do not have the diodes in their pads, yet still be compatible with any recent 5V UARTs.

Interesting how a on-the-surface simple thing like a USB-Serial adapter can get awkward very quick once a few restrictions

are placed on the design. I'd initially expected to not provide 1.8V capability, but I think I cannot avoid it now since it is becoming more prevalent

in SBCs.

As to the real dangers of latch-up, I think you need the advice of someone who understands chip design. My knowledge is just old bits and pieces of the sort that you accumulate over the years. It's possible that they've found ways to mitigate the problem with the lower voltage logic - nowadays it's possible to have many more processing steps than were once economic, so maybe they can create structures where the latch-up happens at a much higher voltage. I still try to avoid excessive levels of overshoot, which is one area where it was sometimes a problem, but maybe I'm living in the past.

If you think the receiver is always going to be operating with TTL levels, then you could just limit the tx signal to about 2V. A simpler way to do that than a transistor is a diode clamp:

That suffers a little from the same problem as the transistor (charge storage slowing things down), so I though I'd try out the speed-up cap again (sorry, bear with me, curiosity beckons). This time we need to 'empty' all three diodes

now it's fast [small-signal diodes can really whizz along if you give them a bit of a nudge], but getting a bit silly in your case where you don't need the speed

As with the transistor, it's not going to drive very well - for good drive you need a balanced [active] output and to start considering termination for longer cables.

Did I mention that I'm really into simulation? I'm like a child in a sweetshop with this new-found toy.

Hi Jon!

We're thinking along the same lines : ) I too was experimenting with speedup using capacitors, although as you say it might be unnecessary. I think from memory the typical UART state machines use a 16x clock (I could be wrong), so there is 1/16 of 1/115200 that I can afford to have in the undefined voltage region.

I think I'm nearing into a design now, but I will do some tests/measurements on some of the popular boards, just to feel comfortable that the final selected values are likely to work with all popular boards and will be safe to accidentally have swapped around indefinitely.

I can't wait to try it out, hopefully over the weekend!

Traditional UARTs were 16x and sampled somewhere in the middle. Your critical edges are on the start bit because they are going to be the reference for the timing of the sampling. I have a vague idea people subsequently developed schemes to sample more than once and do majority voting to avoid the obvious problem of a short supply glitch changing a bit.

The PIC UARTs allow for x4, x16 and x64 (not all devices do all of those). The x4 rate accomodates the faster baud rates where they are getting close to the system clock rate. Not sure where it samples - I'd go for the clock cycle after the centre point if it were me designing it.  Presumably the Atmel parts on Arduinos would be similar. So you have a bit of lattitude at the edge, but not too much (if you want to cater for very fast baud rates).

Have fun with the experimenting. Alternative clamps you might try would be a 2V zener diode or a red LED.