Testpoints for ICT testers

Michael Sansom schrieb:

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

Not to my knowledege.

Ideally I'd like to know the percent of nets covered by testpoints and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

You could write an ULP that collects all net names and then checks which

nets are connected to testpoints (which should be identifiable by a

common prefix, for example). The easiest way to provide the results is a

list containing covered and uncovered net names - and that would also be

sufficient for your decision.

I don't know if such an ULP already exists.

Tilmann

On 12/28/2010 2:12 AM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>> without putting a testpoint component on each net on my schematic?

 

Not to my knowledege.

This is quite unfortunate.  In any engineering company I've ever

participated in of even a moderate size, the insertion of test points is

normally a post processing function, done by the PCB designer who more

often than not is not the engineer who generated the schematic.  The PCB

designer is generally tasked with inserting test points so as to insure

that a minimum fault coverage is achieved during ICT (say 90% perhaps).

  It is generally solely a function of the manufacturing/quality control

people to determine what test coverage level they desire and to insert

the test points to meet that level.  The design engineer generally

neither cares nor wants to be bothered with that information.  Only if

there are particular nets of interest that the design engineer wants to

ensure to be tested at ICT will he explicitly insert test points on the

schematic, and typically this will be for a very small percentage of the

total nets on the board.

Practically, having to insert all testpoints on the schematic results

in a cluttered, less readable schematic since you will in general want

to cover a high percentage of nets (ideally 100%).  If this is not a

planned feature for future versions of Eagle I would encourage CadSoft

to seriously consider it.

I would think you would accomplish this by having a special class of PCB

components which are specifically excluded from consideration when

doing a cross check between the PCB layout and the schematic netlist.

-Michael

On 12/28/2010 10:25 AM, Michael Sansom wrote:

On 12/28/2010 2:12 AM, Tilmann Reh wrote:

>> Michael Sansom schrieb:

>>

>>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>>> without putting a testpoint component on each net on my schematic?

>>

>> Not to my knowledege.

After a few more minutes of consideration, I don't see why Eagle

couldn't treat testpoints exactly the way they currently treat plated

holes.  For instance, on the board I am currently working on, I have

four plated thru mounting hole.  These holes are electrically tied to a

net (GND), and yet they appear nowhere on my schematic.  They were added

during the PCB layout process and have nothing to do with the schematic.

  Like testpoints, they are single port elements, i.e. they make one and

only one connection to a single net, so they do not interfere with the

functionality established by the schematic.

Clearly, Eagle already has a mechanism for handling single port elements

that are added to the PCB manually but not to the schematic.  A

testpoint would simply be a similar element that consisted of a single

non-drilled pad.

Michael Sansom schrieb:

After a few more minutes of consideration, I don't see why Eagle

couldn't treat testpoints exactly the way they currently treat plated

holes.  For instance, on the board I am currently working on, I have

four plated thru mounting hole.  These holes are electrically tied to a

net (GND), and yet they appear nowhere on my schematic.  They were added

during the PCB layout process and have nothing to do with the schematic.

Did you check if the files are still consistent?

  Like testpoints, they are single port elements, i.e. they make one and

only one connection to a single net, so they do not interfere with the

functionality established by the schematic.

 

Clearly, Eagle already has a mechanism for handling single port elements

that are added to the PCB manually but not to the schematic.  A

testpoint would simply be a similar element that consisted of a single

non-drilled pad.

I don't think that Eagle already has such a mechanism. For every

connected pad in the board, you need a pin in the schematic (more or

less visible, Warren already provided an example). And your ICTPs need

pads (normally small round SMDs on one of the outer layers), hence they

need pins in the schematic for a consistent connection.

BTW, it's good to see the testpoints in the schematic, too - and the

schematic designer can easily add them to all nets that shall be

accessible later (and leave the other nets without). Then, the

testpoints can also easily be considered during board layout and you

don't need a third person to add just the testpoints - without detailed

knowledge of the schematic and some layout details, this is somewhat

risky anyway.

Tilmann

Michael Sansom schrieb:

After a few more minutes of consideration, I don't see why Eagle

couldn't treat testpoints exactly the way they currently treat plated

holes.  For instance, on the board I am currently working on, I have

four plated thru mounting hole.  These holes are electrically tied to a

net (GND), and yet they appear nowhere on my schematic.  They were added

during the PCB layout process and have nothing to do with the schematic.

Did you check if the files are still consistent?

  Like testpoints, they are single port elements, i.e. they make one and

only one connection to a single net, so they do not interfere with the

functionality established by the schematic.

 

Clearly, Eagle already has a mechanism for handling single port elements

that are added to the PCB manually but not to the schematic.  A

testpoint would simply be a similar element that consisted of a single

non-drilled pad.

I don't think that Eagle already has such a mechanism. For every

connected pad in the board, you need a pin in the schematic (more or

less visible, Warren already provided an example). And your ICTPs need

pads (normally small round SMDs on one of the outer layers), hence they

need pins in the schematic for a consistent connection.

BTW, it's good to see the testpoints in the schematic, too - and the

schematic designer can easily add them to all nets that shall be

accessible later (and leave the other nets without). Then, the

testpoints can also easily be considered during board layout and you

don't need a third person to add just the testpoints - without detailed

knowledge of the schematic and some layout details, this is somewhat

risky anyway.

Tilmann

On 12/29/2010 2:22 AM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>> After a few more minutes of consideration, I don't see why Eagle

>> couldn't treat testpoints exactly the way they currently treat plated

>> holes.  For instance, on the board I am currently working on, I have

>> four plated thru mounting hole.  These holes are electrically tied to a

>> net (GND), and yet they appear nowhere on my schematic.  They were added

>> during the PCB layout process and have nothing to do with the schematic.

 

Did you check if the files are still consistent?

Yes, the files are still consistent.  Why would they not be?  Is this

not the way the add hole function works.  It seems to work just like the

add via function as far as I can tell.

>>    Like testpoints, they are single port elements, i.e. they make one and

>> only one connection to a single net, so they do not interfere with the

>> functionality established by the schematic.

>>

>> Clearly, Eagle already has a mechanism for handling single port elements

>> that are added to the PCB manually but not to the schematic.  A

>> testpoint would simply be a similar element that consisted of a single

>> non-drilled pad.

 

I don't think that Eagle already has such a mechanism. For every

connected pad in the board, you need a pin in the schematic (more or

less visible, Warren already provided an example). And your ICTPs need

pads (normally small round SMDs on one of the outer layers), hence they

need pins in the schematic for a consistent connection.

Indeed Eagle must have such a mechanism.  Do you have schematic elements

for all the vias on your PCB?  What exactly is the difference between a

via and a test point from a schematic/layout consistency standpoint?  An

ICT test point is simply a via without a drill through it.

 

BTW, it's good to see the testpoints in the schematic, too - and the

schematic designer can easily add them to all nets that shall be

accessible later (and leave the other nets without). Then, the

testpoints can also easily be considered during board layout and you

don't need a third person to add just the testpoints - without detailed

knowledge of the schematic and some layout details, this is somewhat

risky anyway.

 

Tilmann

You are telling me how you think adding test points should work.  I'm

telling you how it does work in the vast majority of companies that I've

ever seen.  I can say that fairly confidently based on the number of

companies that I have worked for as a hardware designer, and the far

greater number of schematics from different companies I have looked

at.  It is very rare for the engineer to place test points on his

schematic for ICT testing (remember, for ICT ideally you want 100% of

nets to have test points).  Generally, engineers will place test points

at signals of interest that he wants to probe with a scope or other

instrumentation for debug.  Generally this will be a small fraction of

the total net count.

At all but the very smallest companies I've worked with, adding test

points for ICT is a post processing operation, in fact it's often not

done until the second or third prototype layout.  As the layout

progresses, it is up to the hardware designer to look at high speed nets

to ensure that adding test points have not created any issues.  In many

schematic capture/layout flows the hardware engineering will add some

sort of "no_test_point" attribute to critical high speed nets to inform

the pcb designer to not insert test points.

Do you really add test point components to all the nets on your schematic?

Michael Sansom schrieb:

>>> After a few more minutes of consideration, I don't see why Eagle

>>> couldn't treat testpoints exactly the way they currently treat plated

>>> holes.  For instance, on the board I am currently working on, I have

>>> four plated thru mounting hole.  These holes are electrically tied to a

>>> net (GND), and yet they appear nowhere on my schematic.  They were added

>>> during the PCB layout process and have nothing to do with the schematic.

>>

>> Did you check if the files are still consistent?

 

Yes, the files are still consistent.  Why would they not be?  Is this

not the way the add hole function works.  It seems to work just like the

add via function as far as I can tell.

I'm very interested about how that works - can you provide a valid (and

DRC-correct) sample of a consistent sch/brd pair?

Indeed Eagle must have such a mechanism.  Do you have schematic elements

for all the vias on your PCB?  What exactly is the difference between a

via and a test point from a schematic/layout consistency standpoint?  An

ICT test point is simply a via without a drill through it.

A hole is just a hole - no electrical connection. So you can simply add

it to the board, without any conflicts with the schematic (as with any

mechanical part).

A via is always related to a drill in it. So while you can simply drop

it where you like to, and attach it to any net you want, it will always

add a drill at that position, and some pad shape in at least one more

signal layer (most often, in all layers).

ICTPs normally are small SMD pads, on one (outer) layer only, without

drill. I don't know of a way to add single pads to a board only and

connect them to a signal without loosing consistency (as with any

package that contains connected pads).

So, if you provide a sample of what you have described above, we might

be able to understand better.

(The only way I can think of that fits your description, is to manually

add the hole, filled circles in (at least) the outer copper layers, and

filled circles in both stop mask layers. For the electrical connection

to a signal, the copper circles could be drawn as two arcs each, or the

DRC complaint of an overlapping ground connection must be ignored. But

you probably don't like to do this on hundreds of testpoints...)

Maybe I didn't notice a new feature of the current version?

You are telling me how you think adding test points should work.  I'm

telling you how it does work in the vast majority of companies that I've

ever seen.

That's not a problem for me - please do it your way. Obviously, our

experience is different here.

Do you really add test point components to all the nets on your schematic?

Yes, if the customer wants me to (BTDT - not a big deal).

No, otherwise, since we don't use ICT inhouse.

Tilmann

On 12/29/2010 11:12 AM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>>>> After a few more minutes of consideration, I don't see why Eagle

>>>> couldn't treat testpoints exactly the way they currently treat plated

>>>> holes.  For instance, on the board I am currently working on, I have

>>>> four plated thru mounting hole.  These holes are electrically tied to a

>>>> net (GND), and yet they appear nowhere on my schematic.  They were added

>>>> during the PCB layout process and have nothing to do with the schematic.

>>>

>>> Did you check if the files are still consistent?

>>

>> Yes, the files are still consistent.  Why would they not be?  Is this

>> not the way the add hole function works.  It seems to work just like the

>> add via function as far as I can tell.

 

I'm very interested about how that works - can you provide a valid (and

DRC-correct) sample of a consistent sch/brd pair?

It is very easy but I slightly misled you (unintentionally).  For the

mounting holes, I simply dropped vias (a really big via as you can

imagine).  I confused myself as I mis-remembered using the hole function

rather than the via function.  So, in my example, I dropped a via at a

certain x,y coordinate then set the drill size (4.8 mm in my example)

and then set the inner and outer layer dimensions appropriately to give

a topside annual ring sized slightly larger than the sheet metal screw

head size than I am using.  Using the NAME function I then tied it to

the desired net (in this case GND) and the "via" makes a perfectly

serviceable electrically connected mounting hole. Almost certainly

someone on this usenet group told me to use this method for mounting

holes.

>> Indeed Eagle must have such a mechanism.  Do you have schematic elements

>> for all the vias on your PCB?  What exactly is the difference between a

>> via and a test point from a schematic/layout consistency standpoint?  An

>> ICT test point is simply a via without a drill through it.

 

A hole is just a hole - no electrical connection. So you can simply add

it to the board, without any conflicts with the schematic (as with any

mechanical part).

Agreed.  See above.  I mis-remembered using the Hole function and

instead had used the Via function.  To be honest when I start a new

layout I usually start with an old layout that had the mounting holes

dropped on it some time back, so it has been awhile since I've had to

drop new mounting holes on a layout.  Normally I just resize, move and

copy the holes on my standard starting layout as needed.

A via is always related to a drill in it. So while you can simply drop

it where you like to, and attach it to any net you want, it will always

add a drill at that position, and some pad shape in at least one more

signal layer (most often, in all layers).

Yes, agreed a via has a drill associated with it.  However, my point is

that Eagle already has a mechanism in place to for the PCB layout tool

to place a "single port" PCB component manually without causing any

consistency issues between the layout and the schematic.  We do it all

the time when we drop vias which of course are not represented on the

schematic (what a nightmare that would be!).

ICTPs normally are small SMD pads, on one (outer) layer only, without

drill. I don't know of a way to add single pads to a board only and

connect them to a signal without loosing consistency (as with any

package that contains connected pads).

Yes, we agree on what a ICTP is.  However, one would think that what

CadSoft already has in place to handle vias could be readily modified to

create an "add testpoint" button and command which would use perhaps 90%

of the code they have currently to handle vias.  A test point really is

just a one sided via with no drill.

So, if you provide a sample of what you have described above, we might

be able to understand better.

See above.

(The only way I can think of that fits your description, is to manually

add the hole, filled circles in (at least) the outer copper layers, and

filled circles in both stop mask layers. For the electrical connection

to a signal, the copper circles could be drawn as two arcs each, or the

DRC complaint of an overlapping ground connection must be ignored. But

you probably don't like to do this on hundreds of testpoints...)

 

Maybe I didn't notice a new feature of the current version?

No, my fault for the confusion.

>> You are telling me how you think adding test points should work.  I'm

>> telling you how it does work in the vast majority of companies that I've

>> ever seen.

 

That's not a problem for me - please do it your way. Obviously, our

experience is different here.

 

>> Do you really add test point components to all the nets on your schematic?

 

Yes, if the customer wants me to (BTDT - not a big deal).

No, otherwise, since we don't use ICT inhouse.

That's probably the root of our difference of opinion on how test points

should be handled.  I have worked at several places where ICT testing

was emphasized, at one place for reliability/quality reasons, at others

for cost reduction reasons (i.e. to minimize the amount of hands-on

functional testing at the end of the manufacturing process.  At my small

company it is the latter reason driving my interest.

Regards,

-Michael

BTW, to give you a bit more information on the work flow I've used in

the past, normally what we do is take the netlist (without ICTPs) and

the BSDL files for all of the JTAG compliant components in the design.

This is then fed into a separate piece of software that looks at the

connectivity in the netlist and the BSDL files and figures out which

nets can be tested with the JTAG scan chain and which can not.  It then

outputs a list of nets that cannot be tested with JTAG and the PCB

designer brings in this list which then places airwire connected test

points for all of the nets not tested with JTAG (unless the net has a

NO_TEST_POINT attribute).  The PCB designer then only has to place these

ICTPs appropriately on the layout and hook them up.

You can readily see that given such a list of JTAG untestable nets, the

appropriate "add testpoint" command in Eagle and the right ULP you could

do exactly the same thing with Eagle.

In fact, if you were really motivated, Eagle's ULP capability would

probably allow you to read the BSDL files directly and let it figure out

itself which nets can be tested via JTAG and which can not, thus

eliminating the need for the external program (which cost several

thousand dollars if I recall correctly).

-Michael

Michael Sansom schrieb:

Yes, agreed a via has a drill associated with it.  However, my point is

that Eagle already has a mechanism in place to for the PCB layout tool

to place a "single port" PCB component manually without causing any

consistency issues between the layout and the schematic.  We do it all

the time when we drop vias which of course are not represented on the

schematic (what a nightmare that would be!).

I think that for EAGLE, vias are /not/ a "single port" component, at

least not intentionally. Currently, vias are just a "vertical segment"

of a track.

Yes, we agree on what a ICTP is.  However, one would think that what

CadSoft already has in place to handle vias could be readily modified to

create an "add testpoint" button and command which would use perhaps 90%

of the code they have currently to handle vias.  A test point really is

just a one sided via with no drill.

I can't tell if it's really a simple modification/addition to the

existing code. Maybe it is - in that case I wouldn't mind if CadSoft

adds this function. (If it's more work, I wouldn't mind either - it's

just that I don't need ICTPs too often. )

>>> Do you really add test point components to all the nets on your schematic?

>>

>> Yes, if the customer wants me to (BTDT - not a big deal).

>> No, otherwise, since we don't use ICT inhouse.

 

That's probably the root of our difference of opinion on how test points

should be handled.  I have worked at several places where ICT testing

was emphasized, at one place for reliability/quality reasons, at others

for cost reduction reasons (i.e. to minimize the amount of hands-on

functional testing at the end of the manufacturing process.  At my small

company it is the latter reason driving my interest.

We already have done designs for customers that wanted/needed every net

on ICTPs for their production tests. As said, it's not a big deal even

if they are visible in the schematic. Maybe this is also related to the

complexity of a board - in our cases, they were not too big. Of course,

these testpoints have to be added in the schematic then, you can't

simply add them later in the board alone.

The cost structure for post-manufacturing test heavily depends on

production volumes - for our rather small quantities, automated ICT

equipment would never calculate. So obviously we are working on

different targets.

Tilmann

"Tilmann Reh" wrote in response

I think that for EAGLE, vias are /not/ a "single port" component, at

least not intentionally. Currently, vias are just a "vertical segment"

of a track.

 

.................

Of course,

these testpoints have to be added in the schematic then, you can't

simply add them later in the board alone.

.............

The issue I see with the simple "SMD-via" approach is identifying this

copper so that a netlist  can show the net does have an ICTP or which point

of many possible (vias or pads or special) is the ICTP

Vias are used as ICTP but  not all of them on a net so at some point the

coords of the ICT-via and its associated net needs to be output. An Eagle

device can get this right with an 'Attribute' but a via cannot do that.

The link I have just referenced in the eagle.suggested.eng

http://www.orcad.com/forums/ShowPost.aspx?PostID=20085 shows competitive

software can assign the test point tag to a via and even a pad stack  It

looks like that can be done separately to the library, in the layout editor

and it looks like this is a Pin attribute set on the board.  Such

granularity  would enable the ICTP/ xy /netlist output to be generated most

easily from the board.

From the article it appears to be useful to 'Lock' the designated via ICTP

which Eagle cannot do currently.

Another consideration is ICTP spacing so potentially the DRC may need an

addition.

E&OE

Warren

On 12/29/2010 2:33 PM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>> Yes, agreed a via has a drill associated with it.  However, my point is

>> that Eagle already has a mechanism in place to for the PCB layout tool

>> to place a "single port" PCB component manually without causing any

>> consistency issues between the layout and the schematic.  We do it all

>> the time when we drop vias which of course are not represented on the

>> schematic (what a nightmare that would be!).

 

I think that for EAGLE, vias are /not/ a "single port" component, at

least not intentionally. Currently, vias are just a "vertical segment"

of a track.

Perhaps not.  But, from an electrical network point of view, they are

single port elements in that they connect to one and only one net.

However they may be implemented by Eagle internally, I still believe

that they would lend themselves to being made into test points without a

great deal of development.

>> Yes, we agree on what a ICTP is.  However, one would think that what

>> CadSoft already has in place to handle vias could be readily modified to

>> create an "add testpoint" button and command which would use perhaps 90%

>> of the code they have currently to handle vias.  A test point really is

>> just a one sided via with no drill.

 

I can't tell if it's really a simple modification/addition to the

existing code. Maybe it is - in that case I wouldn't mind if CadSoft

adds this function. (If it's more work, I wouldn't mind either - it's

just that I don't need ICTPs too often. )

Yes, the degree of difficulty is pure speculation on my part.  Only

CadSoft's developers know now hard or easy this task would be.

>>>> Do you really add test point components to all the nets on your schematic?

>>>

>>> Yes, if the customer wants me to (BTDT - not a big deal).

>>> No, otherwise, since we don't use ICT inhouse.

>>

>> That's probably the root of our difference of opinion on how test points

>> should be handled.  I have worked at several places where ICT testing

>> was emphasized, at one place for reliability/quality reasons, at others

>> for cost reduction reasons (i.e. to minimize the amount of hands-on

>> functional testing at the end of the manufacturing process.  At my small

>> company it is the latter reason driving my interest.

 

We already have done designs for customers that wanted/needed every net

on ICTPs for their production tests. As said, it's not a big deal even

if they are visible in the schematic. Maybe this is also related to the

complexity of a board - in our cases, they were not too big. Of course,

these testpoints have to be added in the schematic then, you can't

simply add them later in the board alone.

 

The cost structure for post-manufacturing test heavily depends on

production volumes - for our rather small quantities, automated ICT

equipment would never calculate. So obviously we are working on

different targets.

I'm looking at board that has a couple of small (thankfully) BGAs, a few

TSSOPS and SOICs and a couple of dozen discrete SMT components (I think

there's about 75 line items on my BOM) and would be made in 10k to 25k

piece monthly volumes (if the product succeeds that is).  The product is

relatively cost sensitive and the cost to build the ICT fixture is

easily amortized, even over the first 1,000 units built.