Testpoints for ICT testers

Michael Sansom wrote on Tue, 28 December 2010 11:25

In any engineering company I've ever

participated in of even a moderate size, the insertion of test points

is

normally a post processing function, done by the PCB designer who more

 

often than not is not the engineer who generated the schematic.

That's a bad idea.  If you have a separate person doing the layout (that

itself is usually not a good idea), then they are usually a draftsman and

not a electrical engineer.  They can't look at the circuit and determine

which nets need to be brought out to be measured or driven externally

during board test.  This process may include a separate production test

engineer, but should always include the circuit designer.

For example, many points connected to a microcontroller don't need to be

connected directly to the tester.  Usually you set up a communication link

to the microcontroller and have it report on the state of signals or drive

them as required.  With a little cleverness, you can infer the operation of

components between the external connections and the micro too sometimes.

The point is, you don't want to blindly connect a pogo pin pad (or whatever

you use to connect to the tester) to every net.  That would add needless

complexity to the board, the tester, and the test process.

Since you have to think about where to connect test points, these should be

on the schematic.  Someone will need to review the test plan, which will

include matching test point on the board with the schematic.  For

troubleshooting you want to know what TP7, for example, is connected to.

Or often you have the reverse case where you want to put a scope probe on a

particular net and want to know if it has a test point, where it is on the

board, and how it's labeled.  In other words, you want test points to show

up in the cross reference list just like any other component.

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

Michael Sansom schrieb:

After a few more minutes of consideration, I don't see why Eagle

couldn't treat testpoints exactly the way they currently treat plated

holes.  For instance, on the board I am currently working on, I have

four plated thru mounting hole.  These holes are electrically tied to a

net (GND), and yet they appear nowhere on my schematic.  They were added

during the PCB layout process and have nothing to do with the schematic.

Did you check if the files are still consistent?

  Like testpoints, they are single port elements, i.e. they make one and

only one connection to a single net, so they do not interfere with the

functionality established by the schematic.

 

Clearly, Eagle already has a mechanism for handling single port elements

that are added to the PCB manually but not to the schematic.  A

testpoint would simply be a similar element that consisted of a single

non-drilled pad.

I don't think that Eagle already has such a mechanism. For every

connected pad in the board, you need a pin in the schematic (more or

less visible, Warren already provided an example). And your ICTPs need

pads (normally small round SMDs on one of the outer layers), hence they

need pins in the schematic for a consistent connection.

BTW, it's good to see the testpoints in the schematic, too - and the

schematic designer can easily add them to all nets that shall be

accessible later (and leave the other nets without). Then, the

testpoints can also easily be considered during board layout and you

don't need a third person to add just the testpoints - without detailed

knowledge of the schematic and some layout details, this is somewhat

risky anyway.

Tilmann

"Michael Sansom" <mssansom@hotmail.com> wrote in message

news:ifb4bo$pg7$1@cheetah.cadsoft.de...

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

Ideally I'd like to know the percent of nets covered by testpoints and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

 

-Michael

Hi Michael

Your requirements to reconcile net names with test pads and have a freely

placeable copper object in the layout editor would likely require a new

special object.

I imagine an object that is similar to the via, but un-drilled and only on

the top or bottom layer, would work to some degree.

What you are left with then is, like a via, only being able to determine if

one of these objects has a net name the same as a wire (routing). More code

is required to determine if they touch.

For now the following idea may be acceptable to you. Doing it this way you

will be able to get all the net name reporting you require, after a ULP is

written.

It does involve the schematic but visually there is only an increase in the

number of 'junction' dots displayed. I would expect that in most instances

you will use the junctions that are already drawn and occasionally  have to

place one on  a net wire.

The test points symbol is mostly on a new User layer which you only display

when needed.

The attached image shows what I mean.

Packages for these test points need placing in the layout editor but there

will be an airwire to assist.

Using Devices with multiple packages you can conveniently "Change Package"

in the board editor to lay down a differently sized test point that is more

appropriate for the available space.

If the test point needs to be away from a trace, this method lets you route

back to the trace as there is a valid net connected (airwire)

The 'Show' command displaying the complete net assists with choosing the

optimum place for the test point.

A ULP could now identify which nets do not attach to an element (your

various test point styles) with a nominated prefix.

One of the current assembly ULPs could provide the XY locations of the test

points and maybe their related net.

HTH

Warren

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end

On 12/28/2010 10:25 AM, Michael Sansom wrote:

On 12/28/2010 2:12 AM, Tilmann Reh wrote:

>> Michael Sansom schrieb:

>>

>>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>>> without putting a testpoint component on each net on my schematic?

>>

>> Not to my knowledege.

After a few more minutes of consideration, I don't see why Eagle

couldn't treat testpoints exactly the way they currently treat plated

holes.  For instance, on the board I am currently working on, I have

four plated thru mounting hole.  These holes are electrically tied to a

net (GND), and yet they appear nowhere on my schematic.  They were added

during the PCB layout process and have nothing to do with the schematic.

  Like testpoints, they are single port elements, i.e. they make one and

only one connection to a single net, so they do not interfere with the

functionality established by the schematic.

Clearly, Eagle already has a mechanism for handling single port elements

that are added to the PCB manually but not to the schematic.  A

testpoint would simply be a similar element that consisted of a single

non-drilled pad.

On 12/28/2010 2:12 AM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>> without putting a testpoint component on each net on my schematic?

 

Not to my knowledege.

This is quite unfortunate.  In any engineering company I've ever

participated in of even a moderate size, the insertion of test points is

normally a post processing function, done by the PCB designer who more

often than not is not the engineer who generated the schematic.  The PCB

designer is generally tasked with inserting test points so as to insure

that a minimum fault coverage is achieved during ICT (say 90% perhaps).

  It is generally solely a function of the manufacturing/quality control

people to determine what test coverage level they desire and to insert

the test points to meet that level.  The design engineer generally

neither cares nor wants to be bothered with that information.  Only if

there are particular nets of interest that the design engineer wants to

ensure to be tested at ICT will he explicitly insert test points on the

schematic, and typically this will be for a very small percentage of the

total nets on the board.

Practically, having to insert all testpoints on the schematic results

in a cluttered, less readable schematic since you will in general want

to cover a high percentage of nets (ideally 100%).  If this is not a

planned feature for future versions of Eagle I would encourage CadSoft

to seriously consider it.

I would think you would accomplish this by having a special class of PCB

components which are specifically excluded from consideration when

doing a cross check between the PCB layout and the schematic netlist.

-Michael

Michael Sansom schrieb:

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

Not to my knowledege.

Ideally I'd like to know the percent of nets covered by testpoints and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

You could write an ULP that collects all net names and then checks which

nets are connected to testpoints (which should be identifiable by a

common prefix, for example). The easiest way to provide the results is a

list containing covered and uncovered net names - and that would also be

sufficient for your decision.

I don't know if such an ULP already exists.

Tilmann