What's all this spartan?
Xilinx offers a comprehensive multi-node portfolio of to address requirements across a wide set of applications. From a state-of-the art, high-performance networking application requiring the highest capacity, bandwidth, and performance, or a low-cost, small footprint FPGA to take software-defined technology to the next level, Xilinx FPGAs and 3D ICs have you covered.
The Spartan®-3 Generation of FPGAs offers a choice of five platforms, each delivering a unique cost-optimized balance of programmable logic, connectivity, and dedicated hard IP for your low-cost applications. Spartan, Spartan-II, Spartan-3, Spartan-6, Spartan-7 are the subs in the main spartan series. Spartan series mainly targets low cost, high-volume applications with a low-power footprint like displays, SDRs, wireless routers and other applications.
The Spartan-6 family is built on a 45 nm, 9-metal layer, dual-oxide process technology. The Spartan-6 was marketed in 2009 as a low-cost option for automotive, wireless communications, flat-panel display and video surveillance applications whereas the Spartan-7 family, built on the 28 nm process used in the other 7-Series FPGAs, was announced in 2015, and became available in 2017.
But should we really move?
Spartan 6 series:
The Spartan-6 LX family encompasses FPGAs with 3.84K to 147K logic cells, as many as 576 I/O pins, 180 DSP slices, and 268 18-Kbit Block RAMs. Spartan-6 LXT FPGAs provide the same range of logic resources as the Spartan-6 LX family members, while providing as many as eight GTP transceivers, each capable of operating at 3.125Gbps, and one PCI Express end point, capable of operating at 2.5Gbps.
Because these FPGAs are 13 years old, and because there’s now an ongoing shortage of older parts like the Spartan-6 family, you may be considering a design migration to newer devices. At the 50,000-foot level, the Xilinx Spartan-7 FPGA family, announced in 2015, might seem like an obvious migration path. However, the jump from Spartan-6 to Spartan-7 FPGAs is not as straightforward as it might seem.
Spartan 7 series:
Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factor packaging for smallest PCB footprint. There is a popular Arty-S7 development board based out of this FPGA!
Differences:
| Feature | Spartan 6 | Spartan 7 |
| Configuration |
• Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits is between 3 Mb and 33 Mb depending on device size and user-design implementation options. • The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. |
• The SSI technology in Spartan-7 enables multiple super logic regions (SLRs) to be combined on a passive interposer layer, using proven manufacturing and assembly techniques from industry leaders, to create a single FPGA with more than ten thousand inter SLR connections, providing ultra-high bandwidth. |
| CLDs, Slices and LUTs |
• Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side as part of two vertical columns. • There are three types of CLB slices in the Spartan-6 architecture: SLICEM, SLICEL, and SLICEX. Each slice contains four LUTs, eight flip-flops, and miscellaneous logic. • The LUTs are for general-purpose combinatorial and sequential logic support. Synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. |
• Real 6-input look-up tables (LUTs) with memory capability within the LUT. • Register and shift register functionality The LUTs in 7 series FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. • Each LUT output can optionally be registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry logic form a slice, and two slices form a configurable logic block (CLB). • Four of the eight flip-flops per slice (one per LUT) can optionally be configured as latches. Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. |
| Clock Management |
• The DCM provides four phases of the input frequency (CLKIN): shifted 0°, 90°, 180°, and 270°. • The PLL can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks in conjunction with the DCMs. The heart of the PLL is a voltage-controlled oscillator (VCO) with a frequency range of 400 MHz to 1,080 MHz, thus spanning more than one octave • In each Spartan-6 FPGA, 16 global-clock lines have the highest fanout and can reach every flip-flop clock. Global clock lines must be driven by global clock buffers, which can also perform glitchless clock multiplexing and the clock enable function. |
• The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). • Each 7 series FPGA has up to 24 clock management tiles (CMTs), each consisting of one mixed-mode clock manager (MMCM) and one phase-locked loop (PLL) • In each 7 series FPGA (except XC7S6 and XC7S15), 32 global clock lines have the highest fanout and can reach every flip-lop clock, clock enable, and set/reset, as well as many logic inputs. • IO clocks are especially fast and serve only I/O logic and serializer/deserializer(SerDes) circuits, as described in the I/O Logic section. The 7 series devices have a direct connection from the MMCM to the I/O for low-jitter, high-performance interfaces. |
| Block RAM | • Every Spartan-6 FPGA has between 12 and 268 dual-port block RAMs, each storing 18Kb. Each block RAM has two completely independent ports that share only the stored data |
• Dual-port 36Kb block RAM with port widths of up to 72 and Programmable FIFO logic. • Built-in optional error correction circuitry Every 7 series FPGA has between 5 and 1,880 dual-port block RAMs, each storing 36Kb. Each block RAM has two completely independent ports that share nothing but the stored data |
| DSP | • Each DSP48A1 slice consists of a dedicated 18 × 18 bit two's complement multiplier and a 48-bit accumulator, both capable of operating at up to 390MHz. | • Each DSP slice fundamentally consists of a dedicated 25 × 18 bit two's complement multiplier and a 48-bit accumulator, both capable of operating up to 741MHz. |
| IO | • The number of I/O pins varies from 102 to 576, depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 3.3V. |
• High-performance SelectIO technology with support for 1,866 Mb/s DDR3. The number of I/O pins varies depending on device and package size. Each I/O is configurable and can comply with a large number of I/O standards. • The HR I/Os offer the widest range of voltage support, from 1.2V to 3.3V. The HP I/Os are optimized for highest performance operation, from 1.2V to 1.8V. |
| Low-Power Gigabit Transceiver |
• All Spartan-6 LXT devices have 2–8 gigabit transceiver circuits. Each GTP transceiver is a combined transmitter and receiver capable of operating at data rates up to 3.2 Gb/s. • The transmitter and receiver are independent circuits that use separate PLLs to multiply the reference frequency input by certain programmable numbers between 2 and 25, to become the bit-serial data clock. • Each GTP transceiver has a large number of user-definable features and parameters. All of these can be defined during device configuration, and many can also be modified during operation. |
• High-performance transceivers capable of up to 6.6 Gb/s (GTP), 12.5 Gb/s (GTX), 13.1 Gb/s (GTH), or 28.05 Gb/s (GTZ) line rates depending on the family, enabling the first single device for 400G implementations. • Ultra-fast serial data transmission to optical modules, between ICs on the same PCB, over the backplane, or over longer distances is becoming increasingly popular and important to enable customer line cards to scale to 100 Gb/s and onwards to 400 Gb/s. • The transceiver count in the 7 series FPGAs ranges from up to 16 transceiver circuits. |
| Encryption | - | • In all 7 series FPGAs (except XC7S6 and XC7S15), the FPGA bitstream, which contains sensitive customer IP, can be protected with 256-bit AES encryption and HMAC/SHA-256 authentication to prevent unauthorized copying of the design. |
| XADC | - |
• Dual 12-bit 1 MSPS analog-to-digital converters (ADCs) with upto 17 flexible and user-configurable analog inputs. • On-chip or external reference option and temperature (±4°C max error) and power supply (±1% max error) sensors • Continuous JTAG access to ADC measurements |
What's further?
Artix 7: Artix®-7 devices provide the highest performance-per-watt fabric, transceiver line rates, DSP processing, and AMS integration in a cost-optimized FPGA. Featuring the Microblaze soft-processor and 1,066Mb/s DDR3 support, the family is the best value for a variety of cost and power-sensitive applications including software-defined radio, machine vision cameras, and low-end wireless backhaul.
Virtex 7: Virtex®-7 FPGAs are optimized for system performance and integration at 28nm and bring best-in-class performance/watt fabric, DSP performance, and I/O bandwidth to your designs. The family is used in an array of applications such as 10G to 100G networking, portable radar, and ASIC Prototyping.
Kintex 7: Kintex®-7 FPGAs provide your designs with the best price/performance/watt at 28nm while giving you high DSP ratios, cost-effective packaging, and support for mainstream standards like PCIe® Gen3 and 10 Gigabit Ethernet. The Kintex-7 family is ideal for applications including 3G and 4G wireless, flat panel displays, and video over IP solutions.
Ultrascale: UltraScale
devices provide the greatest performance and integration at 20nm, including serial I/O bandwidth and logic capacity. As the industry’s only high-end FPGA at the 20nm process node, this family is ideal for applications ranging from 400G networking to large scale ASIC prototyping and emulation.
Ultrascale+: UltraScale+ devices provide the highest performance and integration capabilities in a 14nm/16nm FinFET node. Xilinx 3rd generation 3D ICs use stacked silicon interconnect (SSI) technology to break through the limitations of Moore’s law and deliver the highest signal processing and serial I/O bandwidth to satisfy the most demanding design requirements. It also provides registered inter-die routing lines enabling >600 MHz operation, with abundant and flexible clocking to deliver a virtual monolithic design experience. As the industry's most capable FPGA family, the devices are ideal for compute-intensive applications ranging from 1+Tb/s networking, machine learning, to radar/early-warning systems.
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