This is the first blog in the series of blog I am going to write about Spartan-7 as part of the 7 Ways to Leave Your Spartan-6 FPGA roadtest. In this blog we shall cover the need to migrate from Spartan-6 to Spartan-7, basic difference between Spartan-6 and Spartan-7 and things to be considered when migrating an existing design.
Introduction to Spartan-6 and Spartan-7 series FPGAs
The AMD-Xilinx's Spartan series of FPGA are targeted towards the low cost, high volume applications with a low power footprint. Spartan-6 devices, introduced in 2009 offer industry-leading connectivity features such as high logic-to-pin ratios, small form-factor packaging, MicroBlaze soft processor, and a diverse number of supported I/O protocols. Spartan-6 was based on 45nm technology. These FPGA's were primarily targeted towards a range of advanced bridging applications found in consumer, automotive infotainment solutions, and industrial automation.
Spartan-7 devices introduced in 2010 and built on 28nm technology is the newest addition to the cost-optimized portfolio, offer the best in class performance per watt, along with small form factor packaging to meet the most stringent requirements. Like the Spartan-6, these devices also feature a MicroBlaze soft processor but with higher performance (running over 200 DMIPs with 800Mb/s DDR3 support). Spartan-7 devices also offer newer features like an integrated ADC, dedicated security features, and Q-grade (-40 to +125°C) on all commercial devices. These devices are ideally suited for industrial, consumer, and automotive applications including any-to-any connectivity, sensor fusion, and embedded vision.
The need for migration is triggered mainly by the semiconductor shortage with regards to capacity shortages in older generation process technology (65nm and 45nm). There is also the business need to future proof the products by exploring devices that increases performances and lower power consumption.
Difference between Spartan-6 and Spartan-7 series FPGAs
Configurable Logic Blocks (CLB)
CLB's are the fundamental blocks of the FPGA that allows the user to implement any logical function on the FPGA. The CLBs are made up of slices (can be of the same type, or different). The number and type of slices vary with devices. These slices are made up of Look-up-Tables, registers and multiplexers. A simple logic that we write can be mapped into a single CLBs and for more complex logics, a group of such CLBs can be connected through interconnect logic.
- Has three types of slices, Slice_M, Slice_L and Slice_X.
- Slice_X is the most basic type of logic structure.
Has only two types of slices
- Slice_M - LUT can act as distributed memory or shift registers
- Slice_X needs to be mapped to Slice_L (provides performance improvements)
Block RAMs are one of the fundamental elements of the FPGA and is used for storing data within the FPGA.
- BRAMs are arranged as 18Kb blocks and can be configured as two 9Kb blocks
- BRAMs are arranged as 36Kb blocks which can be configured as two 18Kb memories
During migration, retargeting and mapping to the appropriate BRAMs is done during synthesis stage. Migrating designs to newer S7 devices enhances capabilities like availability of build-in FIFO, cascading Block RAMs, and built-in error correction codes
The DSP blocks support in the implementation of fixed point and floating-point arithmetic for filter design, FFT implementation and other signal processing implementation.
- Spartan-6 provides a DSP48A1 which provides 18x18 signed multiplication
- Spartan-7 Series devices use DSP48E1 which implements a 25x18 signed multiply.
- DSP48E1 enables support for implementing pattern detection and 17-bit shifter structures
- when needed by the application. It can also increase throughput through Single Instruction Multiple Data (SIMD) mode.
As with the previous cases, migration from DSP48A1 to DSP48E1 is done automatically during synthesis stage of Vivado design.
A clock in the FPGA design is responsible for how fast a design runs on the hardware. Understanding the clock architecture is one of the important aspects of the FPGA design. Clocks are generally connected in the design through specialized buffers called clock buffers.
- Spartan-6 provides user with PLL (Phase Locked Loop) and DCM (Digital Clock Managers) for configuring clocks for the design.
- Spartan-7 provides the user with CMT (Clock Management Tiles), PLL's and MMCM for each IO bank.
- Clocking architecture is simpler compared to Spartan-6.
PLL's and DCM's on Spartan-6 can be easily migrated to MMCM on Spartan-7. The buffers BUFH and BUFG can in Spartan-6 will automatically migrated to Spartan-7. Migration of BUFIO2 needs to be done manually.
Having the ability to connect with external memories is important in FPGA designs. As modern design becomes complex and more feature rich (like high bandwidth and high data-rate video application, supporting embedded applications based on Linux), the need for external memories keeps growing. Both Spartan-6 and Spartan-7 provide the ability to interface with memory interface but there are some underlying differences on how this is achieved.
- Spartan-6 implementation uses an integrated memory block.
- So, this uses a lot more IO pins and might be difficult to route pins during PCB design/layout process.
- Spartan-7 uses a Soft IP core to implement the memory controller where only the memory PHY is hardened.
- Having a soft IP core offers flexibility during PCB routing process as it frees up IO pins that can be used for other interfaces.
- Provides support for DDR3, DDR3L, DDR2, and LPDDR2
Transceivers and PCIe are important components when the design is targeted towards high bandwidth applications.
- Provides multi gigabit GTP transceivers with maximum data rate of 3.2Gbps
- Dual-tile implementation
- Tx and Rx should be clocked by the same PLL
- Provides multi gigabit GTP transceivers with maximum data rate of 6/25 Gbps
- Quad-tile implementation
- Tx and Rx can be independently clocked from any PLL
7 Series devices support both PCIe Gen 1 and Gen 2 in the Artix-7 range. This allows the user to benefit from greater performance as bandwidth is significantly increased if desired.
The toolchain refers to the tool or set of tools that are used to create a design, process the outputs (after synthesis, implementation, bitfile generation) and generate the necessary software and executable files that can run on the hardware.
- Uses the ISE, EDK, PlanAhead and SDK tool chain
- Constraints are written in the UCF format
- Vivado and Vitis toolchain
- Besides supporting the pure RTL flow, Vivado enables developers to leverage inbuilt IP library for creating embedded system designs which can run on a softcore processor or a heterogenous SoC.
- Constraints are written in the XDC format based on SDC
- Enables better design analysis and quality of results assessment through detailed reports.
In this blog, we gave a general introduction to the Spartan-6 and Spartan-7 series FPGA's. The need for migration from Spartan-6 to Spartan-7. The difference between the various building blocks of the two series of FPGAs were also discussed from a technical perspective, with an emphasis on how to migrate the design from Spartan-6 to Spartan-7. Overall, with the developments in the toolchain, the migration can be handled by the synthesis engine by itself, but there are specific instances were manual intervention is required to do the migration. The benefits obtained (product longevity, tool chain updates, performance improvements, lower power consumption etc) by migrating to a Spartan-7 outweighs the efforts required to migrate the design from Spartan-6.
- Migrating Spartan 6 Design to 7 Series & Beyond, by Adiuvo Engineering