I'm starting a project log for a wideband 2T2R RF front end built around an AD9361-class transceiver paired with a Zynq-7000 (the same class of platform many SDR boards use). The goal is a working, documented bring-up: stable clocking, a reliable digital link to the PL, calibrated RX/TX, and eventually real EVM and noise-figure numbers. Part 1 covers the three things that decide whether you even get to first base.
（1）Clock plan
Everything in the part is derived from a single reference — on this class of device typically a 40 MHz TCXO. That reference feeds the RF synthesizers (RX/TX LO) and the baseband PLL, which generates the ADC/DAC and data-clock rates. Two practical points:
- Use a TCXO, not a bare crystal. A few ppm of drift is fatal for narrow channels and shows up as frequency error across the whole chain. - The clock tree is coupled. The chosen sample rate (up to 61.44 MS/s at the top end) and the baseband bandwidth (200 kHz to 56 MHz) are configured together with the PLL settings — you don't pick them independently.
（2) Data interface
The transceiver connects to the FPGA over a parallel CMOS or LVDS bus carrying I and Q for both channels, plus a data clock and framing signals. On the Zynq side this lands in the PL and feeds DMA into the PS.
- Decide CMOS vs LVDS up front based on trace count and the rate you need; LVDS is the safer choice at the higher sample rates. - Treat the data interface as a timing-closure problem: meet setup/hold on the bus at your data-clock rate before worrying about RF. A swapped I/Q lane or a missed clock edge is the most common "no samples" cause. - Confirm the link with a simple pattern/loopback before attaching the full DMA path.
（3) The first "is it alive?" sequence
On power-up the device is not ready until an initialization and calibration sequence runs. In practice:
- Apply the reference and boot the part into a known state. - Load the initialization parameters (mode, channels, rate, bandwidth, LO, gains). - Run the tracking calibrations — DC offset, LO leakage, quadrature — and wait for them to report done/pass. Polling status, not a fixed delay, is the reliable way. - Only then read I/Q on RX (or transmit a tone on TX) and check it on a spectrum analyzer / IIO-style tool.
What I learned first
The two things that cost us time were (a) assuming the 70 MHz–6 GHz tuning range meant simultaneous coverage — it's the LO range; you only digitize up to 56 MHz at once — and (b) moving on before the background calibrations had actually settled after an LO change, which lets DC offset and the image drift back.
Next in Part 2: getting RX samples through the DMA into the PS over the 1 GbE/IIO-style path, and the no-OS vs SPI-from-the-PL decision (relevant if your FPGA has no soft processor). I'll post register/status details and the first captured spectra.
Happy to be corrected by anyone who's done this — and if there's a specific part of the bring-up you'd like me to dig into, say so in the comments.
(Disclosure: I work on RF and high-speed data-converter applications, including AD9361-class transceivers. This is a genuine engineering log, not a product pitch.)