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Blog Discussion with Choices of Design for the Arty S7 - The Blinky Project
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  • Author Author: fyaocn
  • Date Created: 20 Jun 2022 5:30 AM Date Created
  • Views 824 views
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Discussion with Choices of Design for the Arty S7 - The Blinky Project

fyaocn
fyaocn
20 Jun 2022

Build a project with the Arty S7-The Blinky Project

1. How many ways to Build one start-up Project ?

With reference to previous comparation between Spartan-6 and Spartan-7, more design choice are available. This blog tries to enlighten as many as choice to complete the job.

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2. About Arty-S7

Before start, a glance on this web page can Programmable Logic - Digilent Reference give clues on where  Spartan-7 is on Digilent Xilinx FPGA family tree, with  256 MB DDR3L, 16 MB QSPI Flash,  2,700 Kb BRAM resources. It is good start point for FPGA exploration as Arty S7 - Digilent Reference.

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This reference page is important for Hardware definition.

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3. Prepare the  software in Windows 10

 It is better to use Vitis selection after  Xilinx_Unified_2022.1_0420_0327_Win64 is started in Windows 10. Refer to Installing Vivado, Vitis, and Digilent Board Files - Digilent Reference

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Install the board is easy now, just press refresh button and find the Arty-S7 board, the hardware definition files shall be installed automatically.

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Then start the Vivado to build the first Project, to blink the leds.

4. Choices of Design and Build one FPGA Project 

4.1 Design Baremetal with basic Logic Gates in Block Design in VIvado

4.2 Design Baremetal with IP integrator in Vivado

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4.3 Design Baremetal with Verilog , System Verilog or VHDL in Vivado

  • Set port in constrain file of .xdc

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create the verilog file blink.v

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with port set according to that of .xdc

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edit the verilog file

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Run synthesis

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Run  implementation

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Create bitstream

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Open hardware manager to connect the Arty-S7 

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Program the Device  with blink.bit file then run the blink project.

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Refer to Getting Started with Vivado for Hardware-Only Designs - Digilent Reference for details.

4.4 Designing with C++ in MicroBlaze core, Vitis

4.5 Desiging with kinds of MicroCore like ARM-M1, RISC-V or MIPS

5. Please leave your idea on this discuss Choices of Design and Build one FPGA Project on Digilent Arty-S7 - Forum - FPGA - element14 Community To correct me if there is anything not right.

Reference:

1. Programmable Logic - Digilent Reference

2. Arty S7 Reference Manual - Digilent Reference

3. Installing Vivado, Vitis, and Digilent Board Files - Digilent Reference

4. Choices of Design and Build one FPGA Project on Digilent Arty-S7 - Forum - FPGA - element14 Community

5. Arm DesignStart FPGA Cortex-M1 Environmental Monitor - Digilent Projects (digilentinc.com)

6. Arm DesignStart FPGA Cortex-M3-Based Robot - Digilent Projects (digilentinc.com)

7. GitHub - OpenXiangShan/XiangShan: Open-source high-performance RISC-V processor

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