Spartan 7 has 36 kb BRAM where as Spartan 6 has 18kb.
Spartan 7 offers BRAM cascading to build bigger memories. Such features are not available in Spartan 6.
Spartan 7 uses Soft memory controller for DDR support whereas Spartan 6 uses Hard memory controller.
In the Spartan-6, the developer is provided with a DSP48A1 which provides 18x18 signed multiplication while Spartan 7 series devices play DSP48E1 which implements a 25x18 signed multiply
capabilities like providing build in FIFO, cascading block RAMs, and built-in error correction codes are available in Spartan 7. These features are not available in Spartan 6.
Architecturally, the Spartan 7 series devices also enables the implementation of an Algorithmic Logic Unit (ALU) and enables support of Single Instruction Multiple Data (SIMD) mode which allows increased throughput. The DSP48E1 is also capable of implementing pattern detection and 17-bit shifter structures as required by the application.
Spartan-6 designs which use either a PLL or DCM_SP will migrate to a MMCM in a 7 series device.
Spartan-6 LXT devices provide the developer with multi-gigabit transceivers in the GTP at a maximum speed of 3.2 Gb/s. 7 series devices which support transceivers can support higher data rates or up to 6/25 Gb/s.
Spartan 7 comes with XADC which is a 1 MSPS ADC which enables the developer to observe the internal supply voltages and die temperature. This feature is not available in Spartan 6.
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