Comparing the differences between the Spartan-6 and Spartan-7 FPGAs
1. The Challenge
It is interesting to understand the Spartan-6 to Spartan-7 FPGA migration by experimenting on it. In my perspective, the prominent improvement is the design concept, from hardware-centered to software-centered. The Vivado IDE shall save the time of developers even with Spartan-6 series support previous ISE,EDK and SDK Tool Chains.
With the improvement in I/O density, data rates, package size, DSP performance, and embedded processors, the architecture can be faster and more resilient .
2. Spartan-6 vs Spartan-7
The Spartan-6 family is based on a 45 nm process and provides developers within the standard LX version 3.8K and 147K logic cells, up to 576 I/O, 180 DSP slices, and 268 18Kb block RAMS.
| Value | Features |
|---|---|
| Programmable System Integration |
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| Increased System Performance |
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| Total Power Reduction |
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| Accelerated Design Productivity |
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The Spartan-7 family is based on a 28 nm process and a MicroBlaze
soft processor running over 200 DMIPs with 800Mb/s DDR3 support built on 28nm technology. Additionally, Spartan-7 devices offer an integrated ADC, dedicated security features, and Q-grade (-40 to +125°C) on all commercial devices.
| Value | Features |
|---|---|
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Programmable System Integration |
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Increased System Performance |
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BOM Cost Reduction |
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Total Power Reduction |
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Accelerated Design Productivity |
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Spartan®-7 devices is Cost-Optimized, offers the best in class performance per watt, with size and performance. Red text above shows key differences.
More shall be take into accounts in migration
2.1Logic - The fundamental element of an FPGA is the logic cell.
Both the Spartan-6 and 7 series have a function generator which consists of a six input Look Up Table (LUT) with two associated flip flops. Several of these function generators and flip flop structures are combined to create a slice. Each slice contains eight function generators and 16 flip flops. Within 7 series devices, there are two types of slices -- Slice_M and Slice_L. While Slice_M and Slice_L are identical between the Spartan-6 and 7 series devices, Spartan-6 devices also have a Slice_X. Slice_X is the most basic logical structure of the three slice configurations.
2.2 Block RAM
One of the largest differences between Spartan-6 and 7 series devices is in the block Ram. Spartan-6 block RAMs are arranged as 18Kb blocks which can be configured as two 9Kb memories. In comparison, 7 series devices provide 36Kb blocks which can be configured as two 18Kb memories.
2.3 DSP
Both Spartan-6 and Spartan 7 provide dedicated DSP slices that enable the developer to implement multiply accumulate functions. In the Spartan-6, the developer is provided with a DSP48A1 which provides 18x18 signed multiplication while 7 series devices play DSP48E1 which implements a 25x18 signed multiply. Architecturally, the DSP48E1 provided in 7 series devices also enables the implementation of an Algorithmic Logic Unit (ALU) and enables support of Single Instruction Multiple Data (SIMD) mode which allows increased throughput. The DSP48E1 is also capable of implementing pattern detection and 17-bit shifter structures as required by the application.
2.4 Clock
The clocking architecture of 7 series devices is significantly simpler than that previously provided in the in Spartan-6 devices.
The Spartan-6 FPGA provides the developer with Digital Clock Managers (DCM) and Phase Locked Loops (PLL) clocking resources. Within a 7 series Clock Management Tile (CMT), MMCM and PLLs are provided and associated with each I/O bank.
2.5 Memory Interfaces
The Spartan-6 implementation uses an integrated memory block whereas 7 series devices use a Soft IP core to implement the memory controller where only the memory PHY is hardened.
2.6 Transceivers and PCIe
Spartan-6 LXT devices provide the developer with multi-gigabit transceivers in the GTP at a maximum speed of 3.2 Gb/s. 7 series devices which support transceivers can support higher data rates or up to 6/25 Gb/s.
2.7 Additional New Features
The 7 series range also introduced new features such as the XADC which is a 1 MSPS ADC which enables the developer to observe the internal supply voltages and die temperature. This can be very useful when implementing self-test and anti-tamper features. The XADC is also able to quantize 16 external differential signals, removing the need for additional low-speed ADCs used in board monitoring. Along with the ability to provide bitstream security, this is also enhanced in the XADC with the provision of AES256 CBC encryption and SHA-256 authentication.
3 Summary
In general , Spartan-6 is Ideally suited for a range of advanced bridging applications found in consumer, automotive infotainment, and industrial automation.
Spartan-7 is more versitile suited for industrial, consumer, and automotive applications including any-to-any connectivity, sensor fusion, and embedded vision.
Reference:
[1] Spartan-7 FPGA Family (xilinx.com)
[2] Spartan-6 FPGA Family (xilinx.com)
[3] Migrating Xilinx Spartan-6 to 7 Series & Beyond (avnet.com)
[4] 7 Series FPGAs Migration: Methodology Guide (UG429) (avnet.com)
