From Spartan 6 to Spartan 7: The journey of hardware as well as software

In this blog, I will compare the differences between the Spartan 6 and Spartan 7 families of the FPGA from Xilinx. Just to give a background, when I started with FPGAs back in 2013, Spartan 3 was the popular FPGA due to its low cost. Now the FPGA family from Xilinx has come a long way from Spartan 3, 3E to 6 and 7. 

There are major differences between Spartan 6 and Spartan 7 FPGA's not just in the hardware but also in the software. In this blog, I will describe both the changes.

First, let's take a look at the Spartan 6 family. The major features of Spartan 6 are as follows -

The spartan 6 family consists of two types of FPGAs - LX, and LXT. The LX devices are optimized for logic and LXT devices are optimized for high-speed serial connectivity. It contains up to 147,443 logic cells and is built on a 45 nm process. It also supports up to 1080 Mb/s of data transfer rate, 3.2 Gb/s of high-speed serial transceiver, and up to 24 mA of current per pin. Apart from this, it also has a maximum of 180 DSP48A1 slices featuring an 18 x 18 multiplier and a 48-bit accumulator for high-performance signal processing and mathematical computations. It also has integrated memory control blocks for DDR2/3/4 and LPDDR RAM. It also supports the MicroBlaze soft processor.

Now coming to the programming part, Spartan 6 can be programmed using the ISE Design tool which is a pretty old software used to program the older FPGAs such as Spartan 3/3E. The major difference here is in the software as well as the files. Before I list out the features, let's understand the design flow of an FPGA.

The FPGA is programmed using a hardware description language. Two such popular languages are VHDL and Verilog. First, a program is written in Verilog or VHDL which describes the logical connection of the blocks in the FPGA. Then a constraints file has to be written which physically maps the input and output pins from the program to the FPGA. While the code remains the same, this physical mapping done using the constraints file has changed in Spartan 7. Since Spartan 7 is supported by a new software called Vivado. Vivado is the latest IDE from Xilinx which supports all the latest FPGA families after Spartan 6.

This is a major change as the file formats have also changed from ISE to Vivado. This means while migrating from Spartan 6 to Spartan 7, you have to change the software as well. And the constraints file in Viavdo is also different from the ISE constraints file.

Coming to Spartan 7 hardware, It has up to 102K logic cells, 160 DSP slices with 25 x 18 multiplier, 48-bit accumulator, and a pre adder and a MicroBlaze CPU. It also offers high-speed serial connectivity of up to 28.05 Gb/s which is almost 9 times that of Spartan 6. Since an FPGA is a digital device, for interacting with the analog world, it needs an ADC. Spartan 7 features an on-chip user configurable 12-bit 1 MSPS ADC which Spartan 6 lacks. This means you can directly connect analog sensors with the Spartan 7.

Spartan 7 also supports PCIe and has a 256-bit AES encryption making the device more secure. Spartan 7 is built on a 25 nm process.

All in all, the spartan 7 family provides upgrades from the Spartan 6 family without adding much to the cost. Spartan 7 is still a low-cost family like the Spartan 6 FPGAs.

The table below summarises the differences between Spartan 6 and Spartan 7 -

Should you migrate to Spartan 7?

Definitely yes. I would say the two major reasons are the ADC and the 256-bit AES encryption. I cannot imagine a single situation where everything is digital, you'll have at least one analog component in your project that will need an ADC interface to use with a digital device such as an FPGA. Having an integrated ADC saves time and reduces the complexity of interfacing an external ADC. tt also reduces the overall PCB size. And in today's world where everything is electronics and mostly wireless, it's good to have strong encryption in your device to prevent it from getting hacked.